產品詳細資料

Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 600 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 183 Architecture Pipeline SNR (dB) 70.9 ENOB (Bits) 11.3 SFDR (dB) 91 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 600 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 183 Architecture Pipeline SNR (dB) 70.9 ENOB (Bits) 11.3 SFDR (dB) 91 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Ultralow power with single 1.8-V Supply, CMOS output:
    • 183 mW Total power at 65 MSPS
    • 277 mW Total power at 125 MSPS
    • 332 mW Total power at 160 MSPS
  • High dynamic performance:
    • 88-dBc SFDR at 170 MHz
    • 71.4-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable gain up to 6 dB for SNR/SFDR trade-off
  • DC offset correction
  • Output interface options:
    • 1.8-V parallel CMOS interface
    • Double data rate (DDR) LVDS with programmable swing:
      • Standard swing: 350 mV
      • Low swing: 200 mV
  • Supports low input clock amplitude down to 200 mVPP
  • Package: VQFN-64 (9.00 mm × 9.00 mm)
  • Ultralow power with single 1.8-V Supply, CMOS output:
    • 183 mW Total power at 65 MSPS
    • 277 mW Total power at 125 MSPS
    • 332 mW Total power at 160 MSPS
  • High dynamic performance:
    • 88-dBc SFDR at 170 MHz
    • 71.4-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable gain up to 6 dB for SNR/SFDR trade-off
  • DC offset correction
  • Output interface options:
    • 1.8-V parallel CMOS interface
    • Double data rate (DDR) LVDS with programmable swing:
      • Standard swing: 350 mV
      • Low swing: 200 mV
  • Supports low input clock amplitude down to 200 mVPP
  • Package: VQFN-64 (9.00 mm × 9.00 mm)

The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit or 12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit or 12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.

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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet ADS42xx Dual-Channel, 14-Bit, 12-Bit, 160, 125, 65 MSPS Ultralow-Power ADC datasheet (Rev. E) PDF | HTML 2023年 2月 14日
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 2012年 7月 10日
Application note High-Speed, Analog-to-Digital Converter Basics 2012年 1月 11日
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
Application note CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
Application note QFN Layout Guidelines 2006年 7月 28日

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ADS4222EVM — ADS4222 雙通道、12 位元、65-MSPS 類比轉數位轉換器評估模組

  • The ADS4222EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4222 device, an extremely low power dual channel 12-bit 65 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a (...)
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    開發模組 (EVM) 的 GUI

    ADS58C28SPIGUI-SW ADS42xxx SPI GUI

    ADS58C28SPIGUI-SW is the installation package for ADS58C28_ADS42xx_GUI which is used to access or write internal registers of ADS58C28 through an on-board USB port.
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    開發模組 (EVM) 的 GUI

    DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

    This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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    模擬型號

    ADS422x, ADS424x IBIS Model (Rev. B)

    SBAM094B.ZIP (40 KB) - IBIS Model
    計算工具

    ANALOG-ENGINEER-CALC PC software analog engineer's calculator

    The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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    設計工具

    SBAC119 TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

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    配置圖

    ADS42XX_58C28EVM DesignPkg (Rev. B)

    SLAC459B.ZIP (6548 KB)
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    VQFN (RGC) 64 Ultra Librarian

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