ADS4249
- Maximum Sample Rate: 250 MSPS
- Ultra-Low Power with Single 1.8-V Supply:
- 560-mW Total Power at 250 MSPS
- High Dynamic Performance:
- 80-dBc SFDR at 170 MHz
- 71.7-dBFS SNR at 170 MHz
- Crosstalk: > 90 dB at 185 MHz
- Programmable Gain up to 6 dB for
SNR/SFDR Trade-off - DC Offset Correction
- Output Interface Options:
- 1.8-V Parallel CMOS Interface
- Double Data Rate (DDR) LVDS with
Programmable Swing:- Standard Swing: 350 mV
- Low Swing: 200 mV
- Supports Low Input Clock Amplitude
Down to 200 mVPP - Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
Lead (QFN) Package
The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.
The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.
The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC datasheet (Rev. E) | PDF | HTML | 2016/1/7 | ||
| * | 使用指南 | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 2012/7/10 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Signal Chain Noise Figure Analysis | 2014/10/29 | ||||
| 設計指南 | TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide | 2013/9/3 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 使用指南 | TIDA-00070 Verified Design Reference Guide | 2013/1/23 | ||||
| 使用指南 | HSDC-SEK-10 | 2013/1/17 | ||||
| 應用說明 | High-Speed, Analog-to-Digital Converter Basics | 2012/1/11 | ||||
| 使用指南 | TSW3725 Evaluation Module | 2011/10/25 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
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使用者可以向 DATACONVERTERPRO-SW 提供自訂模式，以載入到 TI DAC。支援從 (...)
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除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
TIDA-00068 — 具有 DPD 回饋路徑的基地台收發器
The design is for a small cell base station development platform. It provides two real receive paths, two complex transmit paths, and a shared real feedback path. This design has macro basestation performance, but with small cell base station footprint. The current design handles (...)
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For applications where there are bit errors and resulting sample errors (also called sparkle codes, word errors, or code errors), the ability to measure the Error rates caused by these bit errors is important. This FPGA firmware based application note proposes a method to accurately measure these (...)
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TSW1265EVM 是寬頻 RF 轉數位雙接收器解決方案的範例設計，可將高達 125MHz 的頻譜數位化。系統示範了如何使用 ADS4249、LMH6521、LMK0480x 和一個雙混頻器來達成此目標。 此參考 EVM 與擷取卡（例如 TSW1400）一起使用，可用於擷取和分析窄頻和寬頻訊號。 介紹了有關如何更改 LO 和 IF 頻率以滿足不同應用需求的說明。 TIDA-00073 是使用 TSW1265EVM 的硬體實現的。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。