產品詳細資料

Sample rate (max) (Msps) 125 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 1.5 Power consumption (typ) (mW) 310 Architecture Pipeline SNR (dB) 68.8 ENOB (Bits) 11.1 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 125 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 1.5 Power consumption (typ) (mW) 310 Architecture Pipeline SNR (dB) 68.8 ENOB (Bits) 11.1 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGZ) 48 49 mm² 7 x 7
  • Resolution: 12-Bit, 125MSPS
  • Integrated High-Impedance
    Analog Input Buffer:
    • Input Capacitance at dc: 3.5pF
    • Input Resistance at dc: 10kΩ
  • Maximum Sample Rate: 125MSPS
  • Ultralow Power:
    • 1.8V Analog Power: 114mW
    • 3.3V Buffer Power: 96mW
    • I/O Power: 100mW (DDR LVDS)
  • High Dynamic Performance:
    • SNR: 68.3dBFS at 170MHz
    • SFDR: 87dBc at 170MHz
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω Termination
      • 2x Strength: 50Ω Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.

  • Resolution: 12-Bit, 125MSPS
  • Integrated High-Impedance
    Analog Input Buffer:
    • Input Capacitance at dc: 3.5pF
    • Input Resistance at dc: 10kΩ
  • Maximum Sample Rate: 125MSPS
  • Ultralow Power:
    • 1.8V Analog Power: 114mW
    • 3.3V Buffer Power: 96mW
    • I/O Power: 100mW (DDR LVDS)
  • High Dynamic Performance:
    • SNR: 68.3dBFS at 170MHz
    • SFDR: 87dBc at 170MHz
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω Termination
      • 2x Strength: 50Ω Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.

The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C).

The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C).

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重要文件 類型 標題 格式選項 日期
* Data sheet 12-Bit, 125MSPS Ultra-Low Power ADC with Analog Buffer datasheet 2011年 6月 22日
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 2012年 7月 10日
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 2012年 2月 27日
Application note High-Speed, Analog-to-Digital Converter Basics 2012年 1月 11日
Application note CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
Application note QFN Layout Guidelines 2006年 7月 28日

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The ADS41B25EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS41B25 device, an extremely low power 12-bit 125 MSPS analog to digital converter with integrated high-impedance input buffer. The ADC features a configurable parallel DDR LVDS or CMOS (...)

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The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)

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This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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ADS41xx EVM BOM, Schematic, and PCB

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VQFN (RGZ) 48 Ultra Librarian

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