ADS5242
- Maximum Sample Rate: 65MSPS
- 12-Bit Resolution
- No Missing Codes
- Total Power Dissipation
- Internal Reference: 660mW
- External Reference: 594mW
- CMOS Technology
- Simultaneous Sample-and-Hold
- 70.8dBFS SNR at 10MHz IF
- 3.3V Digital/Analog Supply
- Serialized LVDS Outputs
- Integrated Frame and Bit Patterns
- Option to Double LVDS Clock Output Currents
- Four Current Modes for LVDS
- Pin- and Format-Compatible Family
- HTQFP-64 PowerPAD™ Package
- APPLICATIONS
- Portable Ultrasound Systems
- Tape Drives
- Test Equipment
- Optical Networking
- Communications
PowerPAD is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
The ADS5242 is a high-performance, 65MSPS, 4-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.
An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the four data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock.
The ADS5242 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode.
The device is available in an HTQFP-64 PowerPAD package and is specified over a -40°C to +85°C operating range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface datasheet (Rev. C) | 2005/10/19 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x | 2005/2/23 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HTQFP (PAP) | 64 | Ultra Librarian |