SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
There are several factors that go in to the speed of processing an interrupt: the interrupt controller, the processor, and the system latency.
The VIM behaves deterministically (except for synchronizer delay). Table 7-37 shows the latency of the VIM.
Step | Cycles | Note |
---|---|---|
Edge Detection | 2-3 | Synchronizing to VIM Clock |
Interrupt Capture | 1 | |
Prioritization and Vector Read | 1 | IRQ Could be stalled here if an FIQ is reading the Vector RAM |
IRQ/FIQ output asserted |
The next factor is the processor itself
Step | Cycles(1) | Note |
---|---|---|
Take Exception | ||
Store State | Stack system registers etc | |
Read Vector | 1 | Through MMR or VIC interface (for IRQ. VIC interface will be faster) |
Jump to Vector |
The final factor is system latency to access the actually instructions for the ISR. This will be dependent on where the instructions are (cache, TCM, system memory etc) and dependent on the system latency to reach those memories (1 cycle for cache/TCM, System dependent for external memory)