SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | dependences |
---|---|---|---|---|---|---|---|
PCIE0 | PSC0 | PD_PCIE | LPSC_MAIN_PCIE0 | 75 | OFF | YES | LPSC_MAIN_SERDES1 |
Module Instance | Source | Description |
---|---|---|
PCIE0 | PSC0 | PCIE0 reset |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
---|---|---|---|---|---|
PCIE0 | PCIE0_pcie_cpts_comp_0 | EPWM0_epwm_syncin_IN_0 | EPWM0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | DMASS0_INTAGGR_0_intaggr_levi_pend_IN_1 | DMASS0_INTAGGR_0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | GICSS0_spi_IN_49 | GICSS0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | R5FSS0_CORE0_intr_IN_49 | R5FSS0_CORE0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | WKUP_R5FSS0_CORE0_intr_IN_49 | WKUP_R5FSS0_CORE0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_49 | MCU_R5FSS0_CORE0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | C7X256V0_CLEC_gic_spi_IN_49 | C7X256V0_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | C7X256V1_CLEC_gic_spi_IN_49 | C7X256V1_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | TIFS0_nvic_IN_52 | TIFS0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_comp_0 | HSM0_nvic_IN_52 | HSM0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_genf0_0 | TIMESYNC_EVENT_INTROUTER0_in_IN_4 | TIMESYNC_EVENT_INTROUTER0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_hw1_push_0 | TIMESYNC_EVENT_INTROUTER0_in_IN_5 | TIMESYNC_EVENT_INTROUTER0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_pend_0 | GICSS0_spi_IN_121 | GICSS0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_pend_0 | R5FSS0_CORE0_intr_IN_53 | R5FSS0_CORE0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_53 | MCU_R5FSS0_CORE0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_pend_0 | C7X256V0_CLEC_gic_spi_IN_121 | C7X256V0_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_pend_0 | C7X256V1_CLEC_gic_spi_IN_121 | C7X256V1_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_cpts_sync_0 | TIMESYNC_EVENT_INTROUTER0_in_IN_6 | TIMESYNC_EVENT_INTROUTER0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_downstream_pulse_0 | GICSS0_spi_IN_162 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_downstream_pulse_0 | R5FSS0_CORE0_intr_IN_99 | R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_downstream_pulse_0 | WKUP_R5FSS0_CORE0_intr_IN_98 | WKUP_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_downstream_pulse_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_99 | MCU_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_downstream_pulse_0 | C7X256V0_CLEC_gic_spi_IN_162 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_downstream_pulse_0 | C7X256V1_CLEC_gic_spi_IN_162 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_dpa_pulse_0 | GICSS0_spi_IN_163 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_dpa_pulse_0 | R5FSS0_CORE0_intr_IN_126 | R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_dpa_pulse_0 | WKUP_R5FSS0_CORE0_intr_IN_99 | WKUP_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_dpa_pulse_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_126 | MCU_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_dpa_pulse_0 | C7X256V0_CLEC_gic_spi_IN_163 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_dpa_pulse_0 | C7X256V1_CLEC_gic_spi_IN_163 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_ecc0_corr_level_0 | ESM0_esm_lvl_event_IN_180 | ESM0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_ecc0_uncorr_level_0 | ESM0_esm_lvl_event_IN_181 | ESM0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_ecc1_uncorr_level_0 | ESM0_esm_lvl_event_IN_182 | ESM0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_error_pulse_0 | GICSS0_spi_IN_125 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_error_pulse_0 | C7X256V0_CLEC_gic_spi_IN_125 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_error_pulse_0 | C7X256V1_CLEC_gic_spi_IN_125 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_flr_pulse_0 | GICSS0_spi_IN_126 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_flr_pulse_0 | C7X256V0_CLEC_gic_spi_IN_126 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_flr_pulse_0 | C7X256V1_CLEC_gic_spi_IN_126 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_hot_reset_pulse_0 | GICSS0_spi_IN_123 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_hot_reset_pulse_0 | R5FSS0_CORE0_intr_IN_55 | R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_hot_reset_pulse_0 | WKUP_R5FSS0_CORE0_intr_IN_55 | WKUP_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_hot_reset_pulse_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_55 | MCU_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_hot_reset_pulse_0 | C7X256V0_CLEC_gic_spi_IN_123 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_hot_reset_pulse_0 | C7X256V1_CLEC_gic_spi_IN_123 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_legacy_pulse_0 | GICSS0_spi_IN_127 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_legacy_pulse_0 | C7X256V0_CLEC_gic_spi_IN_127 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_legacy_pulse_0 | C7X256V1_CLEC_gic_spi_IN_127 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_link_state_pulse_0 | GICSS0_spi_IN_131 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_link_state_pulse_0 | C7X256V0_CLEC_gic_spi_IN_131 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_link_state_pulse_0 | C7X256V1_CLEC_gic_spi_IN_131 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_local_level_0 | GICSS0_spi_IN_137 | GICSS0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_local_level_0 | C7X256V0_CLEC_gic_spi_IN_137 | C7X256V0_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_local_level_0 | C7X256V1_CLEC_gic_spi_IN_137 | C7X256V1_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_phy_level_0 | GICSS0_spi_IN_142 | GICSS0 | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_phy_level_0 | C7X256V0_CLEC_gic_spi_IN_142 | C7X256V0_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_phy_level_0 | C7X256V1_CLEC_gic_spi_IN_142 | C7X256V1_CLEC | PCIE0 interrupt request | level |
PCIE0 | PCIE0_pcie_ptm_valid_pulse_0 | TIMESYNC_EVENT_INTROUTER0_in_IN_7 | TIMESYNC_EVENT_INTROUTER0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_ptm_valid_pulse_0 | GICSS0_spi_IN_124 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_ptm_valid_pulse_0 | R5FSS0_CORE0_intr_IN_165 | R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_ptm_valid_pulse_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_165 | MCU_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_ptm_valid_pulse_0 | C7X256V0_CLEC_gic_spi_IN_124 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_ptm_valid_pulse_0 | C7X256V1_CLEC_gic_spi_IN_124 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_pwr_state_pulse_0 | GICSS0_spi_IN_122 | GICSS0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_pwr_state_pulse_0 | R5FSS0_CORE0_intr_IN_54 | R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_pwr_state_pulse_0 | WKUP_R5FSS0_CORE0_intr_IN_54 | WKUP_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_pwr_state_pulse_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_54 | MCU_R5FSS0_CORE0 | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_pwr_state_pulse_0 | C7X256V0_CLEC_gic_spi_IN_122 | C7X256V0_CLEC | PCIE0 interrupt request | pulse |
PCIE0 | PCIE0_pcie_pwr_state_pulse_0 | C7X256V1_CLEC_gic_spi_IN_122 | C7X256V1_CLEC | PCIE0 interrupt request | pulse |
Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
---|---|---|---|---|
PCIE0 | PCIE_CBA_CLK | MAIN_SYSCLK0/2 | ||
PCIE_CPTS_RCLK_CLK | MAIN_PLL2_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | ||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV5_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_SYSCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/5 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/50 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/2 | PCIE0_CLKSEL[2:0] | |||
CLK_12M_RC | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
PCIE_LANE0_REFCLK | MAIN_SYSCLK0/4 | |||
HFOSC0_CLKOUT_SERDES | SERDES1_CLKSEL[1:0] | |||
EXT_REFCLK1 | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_SYSCLK0/2 | ||||
MAIN_PLL2_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV5_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_SYSCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/5 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/50 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CLK_12M_RC | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
PCIE_LANE0_RXCLK | MAIN_SYSCLK0/4 | |||
HFOSC0_CLKOUT_SERDES | SERDES1_CLKSEL[1:0] | |||
EXT_REFCLK1 | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_SYSCLK0/2 | ||||
MAIN_PLL2_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV5_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_SYSCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/5 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/50 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CLK_12M_RC | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
PCIE_LANE0_RXFCLK | MAIN_SYSCLK0/4 | |||
HFOSC0_CLKOUT_SERDES | SERDES1_CLKSEL[1:0] | |||
EXT_REFCLK1 | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_SYSCLK0/2 | ||||
MAIN_PLL2_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV5_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_SYSCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/5 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/50 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CLK_12M_RC | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
PCIE_LANE0_TXFCLK | MAIN_SYSCLK0/4 | |||
HFOSC0_CLKOUT_SERDES | SERDES1_CLKSEL[1:0] | |||
EXT_REFCLK1 | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_SYSCLK0/2 | ||||
MAIN_PLL2_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV5_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_SYSCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/5 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/50 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CLK_12M_RC | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
PCIE_LANE0_TXMCLK | MAIN_SYSCLK0/4 | |||
HFOSC0_CLKOUT_SERDES | SERDES1_CLKSEL[1:0] | |||
EXT_REFCLK1 | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_SYSCLK0/2 | ||||
MAIN_PLL2_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV5_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_SYSCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/5 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/50 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CLK_12M_RC | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
MAIN_PBIST_CLK | ||||
PCIE_PM_CLK | CLK_12M_RC |