SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
This table is filled with FIFO index values. RX channels reference a starting and ending 'slot' in this table for each transfer. The actual FIFO accessed by the DMA for each slot is determined by the FIFO index stored in this table. Note: This is a single register that is shared by all RX threads.
Bits | Field | Reset | Description |
---|---|---|---|
31:28 | Entry7 | 7 | RX FIFO Index for slot 7 |
27:24 | Entry6 | 6 | RX FIFO Index for slot 6 |
23:20 | Entry5 | 5 | RX FIFO Index for slot 5 |
19:16 | Entry4 | 4 | RX FIFO Index for slot 4 |
15:12 | Entry3 | 3 | RX FIFO Index for slot 3 |
11:8 | Entry2 | 2 | RX FIFO Index for slot 2 |
7:4 | Entry1 | 1 | RX FIFO Index for slot 1 |
3:0 | Entry0 | 0 | RX FIFO Index for slot 0 |