SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The device GICSS is a TI module that is based on the Arm GIC-500 interrupt controller. The Arm GIC-500 is a high-performance, area-optimized, built-time configurable interrupt controller which detects, manages, and distributes system interrupts to the Arm Cortex-A53 processors in the Compute Cluster.
The Arm GIC-500 is compliant to the Arm GICv3 standard. It only supports cores (such as A53) that implement the Armv8 architecture and the GIC CPU interface with the standard GIC Stream Protocol Interface. The GICSS includes additional logic (TI wrapper) to fully integrate the Arm GIC-500 into the SoC.