The DPHY_RX module supports the
following features:
- Compliant to MIPI D-PHY standard
v1.2
- Supports up to 4 data and 1 clock
lanes
- Supports up to 2.5 Gbps (with
deskew) and 1.5 Gbps (without deskew) per data lane
- Clock Lane Control /
Interface Logic type is CIL-SCNN for HS and low power
receiving:
- (S)
Peripheral
- Clock
- N/A forward,
N/A reverse escape mode features
- Data Lane Control /
Interface Logic type is CIL-SFAN for HS and low power
receiving:
- (S)
Peripheral
- Forward direction
only for high speed mode
- All forward
direction escape mode features are supported
- No reverse
direction escape mode features are supported
- Data lanes can be independently
operated in HS or ULP mode
- Swapping of DP/DN signals within
each clock/data pair (Facilitated by CSI_RX_IF controller)