SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The procedure in Table 12-275 initializes the MCASP serializers transmitters to operate in DIT-mode (S/PDIF-transmission protocol) after a power-on reset (POR).
Before performing MCASP global initialization, If external clock ACLKR is used, it must be running already for proper synchronization of the MCASP_GBLCTL register.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
1. Apply software reset to different MCASP components. | MCASP_GBLCTL[12-8] | 0x00 |
2. Poll the bits to ensure the active reset value (0x00) is successfully latched into the register. | MCASP_GBLCTL[12-8] | =0x00 |
3. Configure the local power management. | MCASP_PWRIDLESYSCONFIG[1-0] IDLE_MODE | 0x1 |
4. Configure the transmit format unit. | See Section 12.5.2.5.1.2.1.1. | |
5. Configure the transmit frame sync generator. | See Section 12.5.2.5.1.2.1.2. | |
6. Configure the transmit clock generator. | See Section 12.5.2.5.1.2.1.3. | |
7. Configure the TDM sequencer—set all slots active. | MCASP_XTDM[31-0] XTDMS | 0xFFFF FFFF |
8. Configure the desired n-th serializer (n=0 to 3) for transmit mode operation.(3) | MCASP_SRCTLn [1-0] SRMOD; n = 0 to 15 | 0x1 |
9. Configure the MCASP pins functionality. | See Section 12.5.2.5.1.2.1.4. | |
10. Enable the MCASP DIT - transmission mode. | MCASP_DITCTL[0] DITEN | 0x1(2) |
11. Configure DIT-specific subframe fields. | See Table 12-280. | |
12. Release from reset state the divider that outputs the AHCLKX clock.(1) | MCASP_GBLCTL[9] XHCLKRST | 0x1 |
13. Poll the bit to ensure that it is successfully latched in the register. | MCASP_GBLCTL[9] XHCLKRST | =0x1 |
14. Release from reset state the divider that outputs the ACLKX clock.(1) | MCASP_GBLCTL[8] XCLKRST | 0x1 |
15. Poll the bit to ensure that it is successfully latched in the register. | MCASP_GBLCTL[8] XCLKRST | =0x1 |