The following features are not supported on this family of devices:
- ARM Architectural Spinlock
Instructions (LDREX,STREX)
- Any use model other than binary mutex (ex.
counting semaphore, lockless programming) -
Spinlock MMR is a single binary 0,1 implemented by
a state machine
- 64 bit accesses - Spinlock MMRs are aligned on
32-bit boundaries meaning a 64 bit access affects
the state of 2 spinlocks