SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The FSS0_OSPI0 module is hereinafter referred to as OSPI module.
This section describes the OSPI external connections (environment).
The OSPI module is primarily intended for fast booting from Octal- and Quad-SPI flash memories. Figure 12-108 shows a typical connection of the OSPI module to an external Octal-SPI flash memory.
Table 12-127 lists and describes the FSS0_OSPI I/O signals.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(2) |
---|---|---|---|---|
FSS0_OSPIi(4) | ||||
DQ0 | OSPIi(4)_D0 | IO | FSS0_OSPIi(4) data input/output 0 | HiZ |
DQ1 | OSPIi(4)_D1 | IO | FSS0_OSPIi(4) data input/output 1 | HiZ |
DQ2 | OSPIi(4)_D2 | IO | FSS0_OSPIi(4) data input/output 2 | HiZ |
DQ3 | OSPIi(4)_D3 | IO | FSS0_OSPIi(4) data input/output 3 | HiZ |
DQ4 | OSPIi(4)_D4 | IO | FSS0_OSPIi(4) data input/output 4 | HiZ |
DQ5 | OSPIi(4)_D5 | IO | FSS0_OSPIi(4) data input/output 5 | HiZ |
DQ6 | OSPIi(4)_D6 | IO | FSS0_OSPIi(4) data input/output 6 | HiZ |
DQ7 | OSPIi(4)_D7 | IO | FSS0_OSPIi(4) data input/output 7 | HiZ |
N_SS_OUT0 | OSPIi(4)_CSn0 | O | FSS0_OSPIi(4) external flash device chip select 0 | 0x1 |
N_SS_OUT1 | OSPIi(4)_CSn1 | O | FSS0_OSPIi(4) external flash device chip select 1 | 0x1 |
N_SS_OUT2 | OSPIi(4)_CSn2 | O | FSS0_OSPIi(4) external flash device chip select 2 | 0x1 |
N_SS_OUT3 | OSPIi(4)_CSn3 | O | FSS0_OSPIi(4) external flash device chip select 3 | 0x1 |
OCLK | OSPIi(4)_CLK | O | FSS0_OSPIi(4) clock output for the external flash device | 0x0 |
OSPI0_LBCLKO | O | FSS0_OSPIi(4) external loopback output | 0x0 | |
DQS | OSPIi(4)_DQS | I(3) | FSS0_OSPIi(4) data strobe / external loopback input | Don't care |
RESET_OUT0 | OSPIi(4)_RESET_OUT0 | O | FSS0_OSPIi(4) reset output 0 for the external flash device | 0x1 |
RESET_OUT1 | OSPIi(4)_RESET_OUT1 | O | FSS0_OSPIi(4) reset output 1 for the external flash device | 0x1 |
ECC_FAIL | OSPIi(4)_ECC_FAIL | I | FSS0_OSPIi(4) ECC status from the external flash device | 0x1 |
Table 12-128 describes the OSPI I/O connectivity to external SPI devices.
Module Pin | I/O(1) | Description | |||
---|---|---|---|---|---|
4-pin(1) SPI - Single Read/Write (SIO) (DATA_XFER_TYPE_EXT_MODE_FLD=0x0) | 4-pin(1) SPI - Dual Read/Write (DATA_XFER_TYPE_EXT_MODE_FLD=0x1) | 6-pin(1) SPI - Quad Read/Write (DATA_XFER_TYPE_EXT_MODE_FLD=0x2) | 11-pin(1) SPI - Octal Read/Write (DATA_XFER_TYPE_EXT_MODE_FLD=0x3) | ||
DQ0 | IO | Used as SPI data output | Used as SPI data input 0 Used as SPI data output 0 | Used as SPI data input 0 Used as SPI data output 0 | Used as SPI data input 0 Used as SPI data output 0 |
DQ1 | IO | Used as SPI data input | Used as SPI data input 1 Used as SPI data output 1 | Used as SPI data input 1 Used as SPI data output 1 | Used as SPI data input 1 Used as SPI data output 1 |
DQ2 | IO | Not used | Not used | Used as SPI data input 2 Used as SPI data output 2 | Used as SPI data input 2 Used as SPI data output 2 |
DQ3 | IO | Not used | Not used | Used as SPI data input 3 Used as SPI data output 3 | Used as SPI data input 3 Used as SPI data output 3 |
DQ4 | IO | Not used | Not used | Not used | Used as SPI data input 4 Used as SPI data output 4 |
DQ5 | IO | Not used | Not used | Not used | Used as SPI data input 5 Used as SPI data output 5 |
DQ6 | IO | Not used | Not used | Not used | Used as SPI data input 6 Used as SPI data output 6 |
DQ7 | IO | Not used | Not used | Not used | Used as SPI data input 7 Used as SPI data output 7 |
DQS | I(2) | Not used | Not used | Not used | Data strobe or loopback clock input |
OCLK | O | Output clock or loopback clock output. For more information, see Table 12-127. | |||
N_SS_OUT0 | O | External SPI device chip-select 0 | |||
N_SS_OUT1 | O | External SPI device chip-select 1 | |||
N_SS_OUT2 | O | External SPI device chip-select 2 | |||
N_SS_OUT3 | O | External SPI device chip-select 3 | |||
RESET_OUT0 | O | External SPI device reset 0 | |||
RESET_OUT1 | O | External SPI device reset 1 | |||
ECC_FAIL | I | External SPI device ECC failure indication |
For OSPI0_CLK, OSPI0_LBCLKO, and OSPI0_DQS signals to work properly, the RXACTIVE bit of the appropriate registers should be set to 0x1 because of retiming purposes.
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.