SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
J722S Interrupt Architecture includes information on how to utilize various interrupts and events in the system and relationships between interrupts and events.
An interrupt is defined as a physical signal which can be routed to the interrupt controller of various processors, which can cause the Interrupt Service Routine (ISR). This physical signal can be either a pulse or level and the polarity can be either negative or positive. And an interrupt is correspondent to an individual wire.
An event is defined as information transported by the event bus or PSI_L bus. Events are coded using an event index. The same event bus or PSI_L bus is used to transport multiple events. An event can also be routed and multiplexed to different locations. Events can’t trigger a processor’s ISR directly. They must go through the Interrupt Aggregator (IA) to convert the event into an interrupt line. For more information, see Interrupt Aggregator (INTAGGR)
The DMA transfer using BCDMA and PktDMA in J722S can only be triggered using an event. The SoC level interrupt could be used as a BCDMA trigger using L2G logic. Interrupts in the SoC level can’t be used to trigger a pktDMA transfer.
Each type of processor has its unique interrupt controller. All A53 cores share a single Generic Interrupt Controller (GIC). Each R5 micro controller has its own dedicated interrupt controller, called Vectored Interrupt Manager (VIM). Please refer to Section 10.2 for the detailed usage.
J722S also contains multiple SoC level interrupt routers. The main function of those SoC level interrupt routers is to provide flexibility to select interrupt sources from a large group of interrupt sources. Many places use this feature, such as GPIO interrupts and some time synchronization related interrupts.
J722S contains two ESM modules. ESM is used to consolidate/monitor the error events in the device. In this document, ESM may also be referred to as ESM0.
J722S also has some chip level glue logic to convert some miscellaneous signals used as interrupt sources. Those miscellaneous signals are normally self-clear signals and do not need to clear after the Interrupt Service Routine (ISR) like the normal interrupts generated by the peripherals.
Figure 10-1 shows the high level interrupt architecture in J722S.