SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Interrupt Input Line | Interrupt ID | Source Interrupt |
---|---|---|
R5FSS0_CORE0_INTR_IN_1 | 1 | SMS0_AESEIP38T_0_AES_SINTREQUEST_P_0 |
R5FSS0_CORE0_INTR_IN_2 | 2 | SMS0_AESEIP38T_0_AES_SINTREQUEST_S_0 |
R5FSS0_CORE0_INTR_IN_4 | 4 | R5FSS0_CORE0_EXP_INTR_0 |
R5FSS0_CORE0_INTR_IN_5 | 5 | SAM67_DMPAC_WRAP0_DMPAC_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_6 | 6 | SAM67_DMPAC_WRAP0_DMPAC_LEVEL_1 |
R5FSS0_CORE0_INTR_IN_7 | 7 | SA3_SS0_INTAGGR_0_INTAGGR_VINTR_7 |
R5FSS0_CORE0_INTR_IN_8 | 8 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_32 |
R5FSS0_CORE0_INTR_IN_9 | 9 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_33 |
R5FSS0_CORE0_INTR_IN_10 | 10 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_34 |
R5FSS0_CORE0_INTR_IN_11 | 11 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_35 |
R5FSS0_CORE0_INTR_IN_12 | 12 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_36 |
R5FSS0_CORE0_INTR_IN_13 | 13 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_37 |
R5FSS0_CORE0_INTR_IN_14 | 14 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_38 |
R5FSS0_CORE0_INTR_IN_15 | 15 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_39 |
R5FSS0_CORE0_INTR_IN_16 | 16 | SA3_SS0_SA_UL_0_SA_UL_PKA_0 |
R5FSS0_CORE0_INTR_IN_17 | 17 | SA3_SS0_SA_UL_0_SA_UL_TRNG_0 |
R5FSS0_CORE0_INTR_IN_19 | 19 | SMS0_TIFS_CBASS_0_FW_EXCEPTION_INTR_0 |
R5FSS0_CORE0_INTR_IN_20 | 20 | SMS0_COMMON_0_COMBINED_SEC_IN_0 |
R5FSS0_CORE0_INTR_IN_21 | 21 | SMS0_HSM_CBASS_0_FW_EXCEPTION_INTR_0 |
R5FSS0_CORE0_INTR_IN_22 | 22 | GLUELOGIC_GPU_GPIO_REQACK_GLUE_GPU_GPIO_ACKINT_LVL_0 |
R5FSS0_CORE0_INTR_IN_23 | 23 | GLUELOGIC_GPU_GPIO_REQACK_GLUE_GPU_GPIO_REQINT_LVL_0 |
R5FSS0_CORE0_INTR_IN_24 | 24 | TIMER0_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_25 | 25 | TIMER1_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_26 | 26 | TIMER2_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_27 | 27 | TIMER3_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_28 | 28 | TIMER4_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_29 | 29 | TIMER5_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_30 | 30 | RTI8_INTR_WWD_0 |
R5FSS0_CORE0_INTR_IN_31 | 31 | GLUELOGIC_MCU_CBASS_INTR_OR_GLUE_OUT_0 |
R5FSS0_CORE0_INTR_IN_32 | 32 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_12 |
R5FSS0_CORE0_INTR_IN_33 | 33 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_13 |
R5FSS0_CORE0_INTR_IN_34 | 34 | TIMER6_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_35 | 35 | TIMER7_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_36 | 36 | EPWM0_EPWM_ETINT_0 |
R5FSS0_CORE0_INTR_IN_37 | 37 | EPWM1_EPWM_ETINT_0 |
R5FSS0_CORE0_INTR_IN_38 | 38 | EPWM2_EPWM_ETINT_0 |
R5FSS0_CORE0_INTR_IN_39 | 39 | GLUELOGIC_MCU_ACCESS_ERR_INTR_GLUE_OUT_0 |
R5FSS0_CORE0_INTR_IN_40 | 40 | DSS0_DISPC_INTR_REQ_0_0 |
R5FSS0_CORE0_INTR_IN_41 | 41 | DSS0_DISPC_INTR_REQ_1_0 |
R5FSS0_CORE0_INTR_IN_42 | 42 | MCU_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_43 | 43 | MCU_MCAN0_MCANSS_MCAN_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_44 | 44 | MCU_MCAN0_MCANSS_MCAN_LVL_INT_1 |
R5FSS0_CORE0_INTR_IN_45 | 45 | MCU_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_46 | 46 | MCU_MCAN1_MCANSS_MCAN_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_47 | 47 | MCU_MCAN1_MCANSS_MCAN_LVL_INT_1 |
R5FSS0_CORE0_INTR_IN_48 | 48 | CPSW0_CPTS_COMP_0 |
R5FSS0_CORE0_INTR_IN_49 | 49 | PCIE0_PCIE_CPTS_COMP_0 |
R5FSS0_CORE0_INTR_IN_50 | 50 | CSI_TX_IF0_CSI_INTERRUPT_0 |
R5FSS0_CORE0_INTR_IN_51 | 51 | CSI_TX_IF0_CSI_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_52 | 52 | USB1_OTGIRQ_0 |
R5FSS0_CORE0_INTR_IN_53 | 53 | PCIE0_PCIE_CPTS_PEND_0 |
R5FSS0_CORE0_INTR_IN_54 | 54 | PCIE0_PCIE_PWR_STATE_PULSE_0 |
R5FSS0_CORE0_INTR_IN_55 | 55 | PCIE0_PCIE_HOT_RESET_PULSE_0 |
R5FSS0_CORE0_INTR_IN_56 | 56 | MAIN_GPIOMUX_INTROUTER0_OUTP_20 |
R5FSS0_CORE0_INTR_IN_57 | 57 | MAIN_GPIOMUX_INTROUTER0_OUTP_21 |
R5FSS0_CORE0_INTR_IN_58 | 58 | MAIN_GPIOMUX_INTROUTER0_OUTP_32 |
R5FSS0_CORE0_INTR_IN_59 | 59 | MAIN_GPIOMUX_INTROUTER0_OUTP_33 |
R5FSS0_CORE0_INTR_IN_60 | 60 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_14 |
R5FSS0_CORE0_INTR_IN_61 | 61 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_15 |
R5FSS0_CORE0_INTR_IN_63 | 63 | MCAN1_MCANSS_MCAN_LVL_INT_1 |
R5FSS0_CORE0_INTR_IN_64 | 64 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_152 |
R5FSS0_CORE0_INTR_IN_65 | 65 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_153 |
R5FSS0_CORE0_INTR_IN_66 | 66 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_154 |
R5FSS0_CORE0_INTR_IN_67 | 67 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_155 |
R5FSS0_CORE0_INTR_IN_68 | 68 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_156 |
R5FSS0_CORE0_INTR_IN_69 | 69 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_157 |
R5FSS0_CORE0_INTR_IN_70 | 70 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_158 |
R5FSS0_CORE0_INTR_IN_71 | 71 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_159 |
R5FSS0_CORE0_INTR_IN_72 | 72 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_160 |
R5FSS0_CORE0_INTR_IN_73 | 73 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_161 |
R5FSS0_CORE0_INTR_IN_74 | 74 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_162 |
R5FSS0_CORE0_INTR_IN_75 | 75 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_163 |
R5FSS0_CORE0_INTR_IN_76 | 76 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_164 |
R5FSS0_CORE0_INTR_IN_77 | 77 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_165 |
R5FSS0_CORE0_INTR_IN_78 | 78 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_166 |
R5FSS0_CORE0_INTR_IN_79 | 79 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_167 |
R5FSS0_CORE0_INTR_IN_80 | 80 | EPWM0_EPWM_TRIPZINT_0 |
R5FSS0_CORE0_INTR_IN_81 | 81 | EPWM1_EPWM_TRIPZINT_0 |
R5FSS0_CORE0_INTR_IN_82 | 82 | EPWM2_EPWM_TRIPZINT_0 |
R5FSS0_CORE0_INTR_IN_83 | 83 | ECAP0_ECAP_INT_0 |
R5FSS0_CORE0_INTR_IN_84 | 84 | ECAP1_ECAP_INT_0 |
R5FSS0_CORE0_INTR_IN_85 | 85 | ECAP2_ECAP_INT_0 |
R5FSS0_CORE0_INTR_IN_86 | 86 | EQEP0_EQEP_INT_0 |
R5FSS0_CORE0_INTR_IN_87 | 87 | EQEP1_EQEP_INT_0 |
R5FSS0_CORE0_INTR_IN_88 | 88 | EQEP2_EQEP_INT_0 |
R5FSS0_CORE0_INTR_IN_90 | 90 | R5FSS0_COMMON0_COMMRX_LEVEL_0_0 |
R5FSS0_CORE0_INTR_IN_91 | 91 | R5FSS0_COMMON0_COMMTX_LEVEL_0_0 |
R5FSS0_CORE0_INTR_IN_92 | 92 | DSS1_DISPC_INTR_REQ_0_0 |
R5FSS0_CORE0_INTR_IN_93 | 93 | DSS1_DISPC_INTR_REQ_1_0 |
R5FSS0_CORE0_INTR_IN_94 | 94 | R5FSS0_CORE0_PMU_0 |
R5FSS0_CORE0_INTR_IN_95 | 95 | R5FSS0_CORE0_VALFIQ_0 |
R5FSS0_CORE0_INTR_IN_96 | 96 | R5FSS0_CORE0_VALIRQ_0 |
R5FSS0_CORE0_INTR_IN_97 | 97 | WKUP_RTCSS0_RTC_EVENT_PEND_0 |
R5FSS0_CORE0_INTR_IN_99 | 99 | PCIE0_PCIE_DOWNSTREAM_PULSE_0 |
R5FSS0_CORE0_INTR_IN_100 | 100 | JPGENC0_IRQ_0 |
R5FSS0_CORE0_INTR_IN_103 | 103 | GPMC0_GPMC_SINTERRUPT_0 |
R5FSS0_CORE0_INTR_IN_104 | 104 | MAIN_GPIOMUX_INTROUTER0_OUTP_16 |
R5FSS0_CORE0_INTR_IN_105 | 105 | MAIN_GPIOMUX_INTROUTER0_OUTP_17 |
R5FSS0_CORE0_INTR_IN_106 | 106 | MAIN_GPIOMUX_INTROUTER0_OUTP_18 |
R5FSS0_CORE0_INTR_IN_107 | 107 | MAIN_GPIOMUX_INTROUTER0_OUTP_19 |
R5FSS0_CORE0_INTR_IN_108 | 108 | MCU_DCC0_INTR_DONE_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_109 | 109 | GLUELOGIC_MAIN_DCC_DONE_GLUE_DCC_DONE_0 |
R5FSS0_CORE0_INTR_IN_110 | 110 | MCAN1_MCANSS_MCAN_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_111 | 111 | SMS0_RAT_1_EXP_INTR_0 |
R5FSS0_CORE0_INTR_IN_112 | 112 | SMS0_RAT_0_EXP_INTR_0 |
R5FSS0_CORE0_INTR_IN_113 | 113 | GLUELOGICN_MAIN_PBIST_CPU_GLUE_OUT_0 |
R5FSS0_CORE0_INTR_IN_114 | 114 | GLUELOGIC_WKUP_PBIST_CPUINTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_115 | 115 | MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_3 |
R5FSS0_CORE0_INTR_IN_116 | 116 | MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_3 |
R5FSS0_CORE0_INTR_IN_117 | 117 | MCASP3_XMIT_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_118 | 118 | MCASP3_REC_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_119 | 119 | MCRC64_0_INT_MCRC_0 |
R5FSS0_CORE0_INTR_IN_120 | 120 | MCASP0_REC_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_121 | 121 | MCASP0_XMIT_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_122 | 122 | MCASP1_REC_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_123 | 123 | MCASP1_XMIT_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_124 | 124 | MCASP2_REC_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_125 | 125 | MCASP2_XMIT_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_126 | 126 | PCIE0_PCIE_DPA_PULSE_0 |
R5FSS0_CORE0_INTR_IN_128 | 128 | GLUELOGIC_SOC_ACCESS_ERR_INTR_GLUE_OUT_0 |
R5FSS0_CORE0_INTR_IN_129 | 129 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_24 |
R5FSS0_CORE0_INTR_IN_130 | 130 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_25 |
R5FSS0_CORE0_INTR_IN_131 | 131 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_26 |
R5FSS0_CORE0_INTR_IN_132 | 132 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_27 |
R5FSS0_CORE0_INTR_IN_133 | 133 | CODEC0_VPU_WAVE521CL_INTR_0 |
R5FSS0_CORE0_INTR_IN_134 | 134 | CPSW0_EVNT_PEND_0 |
R5FSS0_CORE0_INTR_IN_135 | 135 | CPSW0_MDIO_PEND_0 |
R5FSS0_CORE0_INTR_IN_136 | 136 | CPSW0_STAT_PEND_0 |
R5FSS0_CORE0_INTR_IN_137 | 137 | MCU_DCC1_INTR_DONE_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_138 | 138 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_28 |
R5FSS0_CORE0_INTR_IN_139 | 139 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_29 |
R5FSS0_CORE0_INTR_IN_140 | 140 | WKUP_ESM0_ESM_INT_CFG_LVL_0 |
R5FSS0_CORE0_INTR_IN_141 | 141 | WKUP_ESM0_ESM_INT_HI_LVL_0 |
R5FSS0_CORE0_INTR_IN_142 | 142 | WKUP_ESM0_ESM_INT_LOW_LVL_0 |
R5FSS0_CORE0_INTR_IN_143 | 143 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_30 |
R5FSS0_CORE0_INTR_IN_144 | 144 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_31 |
R5FSS0_CORE0_INTR_IN_145 | 145 | WKUP_PSC0_PSC_ALLINT_0 |
R5FSS0_CORE0_INTR_IN_146 | 146 | PSC0_PSC_ALLINT_0 |
R5FSS0_CORE0_INTR_IN_147 | 147 | GLUELOGIC_SOC_CBASS_ERR_INTR_GLUE_MAIN_CBASS_AGG_ERR_INTR_0 |
R5FSS0_CORE0_INTR_IN_149 | 149 | MCU_PBIST0_DFT_PBIST_CPU_0 |
R5FSS0_CORE0_INTR_IN_150 | 150 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_23 |
R5FSS0_CORE0_INTR_IN_151 | 151 | DDR32SS0_DDRSS_CONTROLLER_0 |
R5FSS0_CORE0_INTR_IN_152 | 152 | GLUELOGIC_MGASKET_INTR_GLUE_OUT_0 |
R5FSS0_CORE0_INTR_IN_153 | 153 | GLUELOGIC_SGASKET_INTR_GLUE_OUT_0 |
R5FSS0_CORE0_INTR_IN_154 | 154 | SERDES_10G1_PHY_PWR_TIMEOUT_LVL_0 |
R5FSS0_CORE0_INTR_IN_155 | 155 | CSI_RX_IF3_CSI_ERR_IRQ_0 |
R5FSS0_CORE0_INTR_IN_156 | 156 | CSI_RX_IF3_CSI_IRQ_0 |
R5FSS0_CORE0_INTR_IN_157 | 157 | CSI_RX_IF3_CSI_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_158 | 158 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_14 |
R5FSS0_CORE0_INTR_IN_159 | 159 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_15 |
R5FSS0_CORE0_INTR_IN_160 | 160 | DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_22 |
R5FSS0_CORE0_INTR_IN_161 | 161 | MMCSD0_EMMCSS_INTR_0 |
R5FSS0_CORE0_INTR_IN_162 | 162 | MMCSD1_EMMCSDSS_INTR_0 |
R5FSS0_CORE0_INTR_IN_163 | 163 | MMCSD2_EMMCSDSS_INTR_0 |
R5FSS0_CORE0_INTR_IN_164 | 164 | ELM0_ELM_POROCPSINTERRUPT_LVL_0 |
R5FSS0_CORE0_INTR_IN_165 | 165 | PCIE0_PCIE_PTM_VALID_PULSE_0 |
R5FSS0_CORE0_INTR_IN_166 | 166 | SERDES_10G0_PHY_PWR_TIMEOUT_LVL_0 |
R5FSS0_CORE0_INTR_IN_167 | 167 | ESM0_ESM_INT_CFG_LVL_0 |
R5FSS0_CORE0_INTR_IN_168 | 168 | ESM0_ESM_INT_HI_LVL_0 |
R5FSS0_CORE0_INTR_IN_169 | 169 | ESM0_ESM_INT_LOW_LVL_0 |
R5FSS0_CORE0_INTR_IN_170 | 170 | CSI_RX_IF0_CSI_ERR_IRQ_0 |
R5FSS0_CORE0_INTR_IN_171 | 171 | FSS0_OSPI_0_OSPI_LVL_INTR_0 |
R5FSS0_CORE0_INTR_IN_172 | 172 | CSI_RX_IF1_CSI_ERR_IRQ_0 |
R5FSS0_CORE0_INTR_IN_173 | 173 | CSI_RX_IF0_CSI_IRQ_0 |
R5FSS0_CORE0_INTR_IN_174 | 174 | CSI_RX_IF0_CSI_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_175 | 175 | R5FSS0_CORE0_CTI_0 |
R5FSS0_CORE0_INTR_IN_176 | 176 | CSI_RX_IF1_CSI_IRQ_0 |
R5FSS0_CORE0_INTR_IN_177 | 177 | DDPA0_DDPA_INTR_0 |
R5FSS0_CORE0_INTR_IN_178 | 178 | VPAC0_VPAC_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_179 | 179 | VPAC0_VPAC_LEVEL_1 |
R5FSS0_CORE0_INTR_IN_180 | 180 | VPAC0_VPAC_LEVEL_2 |
R5FSS0_CORE0_INTR_IN_181 | 181 | DDR32SS0_DDRSS_PLL_FREQ_CHANGE_REQ_0 |
R5FSS0_CORE0_INTR_IN_182 | 182 | VPAC0_VPAC_LEVEL_3 |
R5FSS0_CORE0_INTR_IN_183 | 183 | WKUP_VTM0_THERM_LVL_GT_TH1_INTR_0 |
R5FSS0_CORE0_INTR_IN_184 | 184 | WKUP_VTM0_THERM_LVL_GT_TH2_INTR_0 |
R5FSS0_CORE0_INTR_IN_185 | 185 | WKUP_VTM0_THERM_LVL_LT_TH0_INTR_0 |
R5FSS0_CORE0_INTR_IN_186 | 186 | MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_187 | 187 | MCAN0_MCANSS_MCAN_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_188 | 188 | MCAN0_MCANSS_MCAN_LVL_INT_1 |
R5FSS0_CORE0_INTR_IN_189 | 189 | VPAC0_VPAC_LEVEL_4 |
R5FSS0_CORE0_INTR_IN_190 | 190 | WKUP_I2C0_POINTRPEND_0 |
R5FSS0_CORE0_INTR_IN_191 | 191 | VPAC0_VPAC_LEVEL_5 |
R5FSS0_CORE0_INTR_IN_192 | 192 | MCU_MCRC64_0_INT_MCRC_0 |
R5FSS0_CORE0_INTR_IN_193 | 193 | I2C0_POINTRPEND_0 |
R5FSS0_CORE0_INTR_IN_194 | 194 | I2C1_POINTRPEND_0 |
R5FSS0_CORE0_INTR_IN_195 | 195 | I2C2_POINTRPEND_0 |
R5FSS0_CORE0_INTR_IN_196 | 196 | I2C3_POINTRPEND_0 |
R5FSS0_CORE0_INTR_IN_197 | 197 | MCU_I2C0_POINTRPEND_0 |
R5FSS0_CORE0_INTR_IN_198 | 198 | CSI_RX_IF2_CSI_ERR_IRQ_0 |
R5FSS0_CORE0_INTR_IN_199 | 199 | CSI_RX_IF2_CSI_IRQ_0 |
R5FSS0_CORE0_INTR_IN_200 | 200 | CSI_RX_IF2_CSI_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_201 | 201 | DEBUGSS0_AQCMPINTR_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_202 | 202 | DEBUGSS0_CTM_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_203 | 203 | GLUELOGIC_GLUE_EXT_INTN_OUT_0 |
R5FSS0_CORE0_INTR_IN_204 | 204 | MCSPI0_INTR_SPI_0 |
R5FSS0_CORE0_INTR_IN_205 | 205 | MCSPI1_INTR_SPI_0 |
R5FSS0_CORE0_INTR_IN_206 | 206 | MCSPI2_INTR_SPI_0 |
R5FSS0_CORE0_INTR_IN_207 | 207 | MCU_MCSPI0_INTR_SPI_0 |
R5FSS0_CORE0_INTR_IN_208 | 208 | MCU_MCSPI1_INTR_SPI_0 |
R5FSS0_CORE0_INTR_IN_209 | 209 | CSI_RX_IF1_CSI_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_210 | 210 | UART0_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_211 | 211 | UART1_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_212 | 212 | UART2_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_213 | 213 | UART3_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_214 | 214 | UART4_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_215 | 215 | UART5_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_216 | 216 | UART6_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_217 | 217 | MCU_UART0_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_218 | 218 | DSS_DSI0_DSI_0_FUNC_INTR_0 |
R5FSS0_CORE0_INTR_IN_219 | 219 | WKUP_UART0_USART_IRQ_0 |
R5FSS0_CORE0_INTR_IN_220 | 220 | USB0_IRQ_0 |
R5FSS0_CORE0_INTR_IN_221 | 221 | USB0_IRQ_1 |
R5FSS0_CORE0_INTR_IN_222 | 222 | USB0_IRQ_2 |
R5FSS0_CORE0_INTR_IN_223 | 223 | USB0_IRQ_3 |
R5FSS0_CORE0_INTR_IN_224 | 224 | USB0_IRQ_4 |
R5FSS0_CORE0_INTR_IN_225 | 225 | USB0_IRQ_5 |
R5FSS0_CORE0_INTR_IN_226 | 226 | USB0_IRQ_6 |
R5FSS0_CORE0_INTR_IN_227 | 227 | USB0_IRQ_7 |
R5FSS0_CORE0_INTR_IN_228 | 228 | USB0_MISC_LEVEL_0 |
R5FSS0_CORE0_INTR_IN_229 | 229 | MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
R5FSS0_CORE0_INTR_IN_230 | 230 | USB1_IRQ_0 |
R5FSS0_CORE0_INTR_IN_231 | 231 | USB1_IRQ_1 |
R5FSS0_CORE0_INTR_IN_232 | 232 | USB1_IRQ_2 |
R5FSS0_CORE0_INTR_IN_233 | 233 | USB1_IRQ_3 |
R5FSS0_CORE0_INTR_IN_234 | 234 | USB1_IRQ_4 |
R5FSS0_CORE0_INTR_IN_235 | 235 | USB1_IRQ_5 |
R5FSS0_CORE0_INTR_IN_236 | 236 | USB1_IRQ_6 |
R5FSS0_CORE0_INTR_IN_237 | 237 | USB1_IRQ_7 |
R5FSS0_CORE0_INTR_IN_238 | 238 | USB1_HOST_SYSTEM_ERROR_0 |
R5FSS0_CORE0_INTR_IN_239 | 239 | I2C4_POINTRPEND_0 |
R5FSS0_CORE0_INTR_IN_240 | 240 | MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_3 |
R5FSS0_CORE0_INTR_IN_241 | 241 | MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_3 |
R5FSS0_CORE0_INTR_IN_242 | 242 | MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_3 |
R5FSS0_CORE0_INTR_IN_243 | 243 | MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_3 |
R5FSS0_CORE0_INTR_IN_244 | 244 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_24 |
R5FSS0_CORE0_INTR_IN_245 | 245 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_25 |
R5FSS0_CORE0_INTR_IN_246 | 246 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_26 |
R5FSS0_CORE0_INTR_IN_247 | 247 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_27 |
R5FSS0_CORE0_INTR_IN_248 | 248 | GPU0_GPU_PWRCTRL_REQ_0 |
R5FSS0_CORE0_INTR_IN_249 | 249 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_24 |
R5FSS0_CORE0_INTR_IN_250 | 250 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_25 |
R5FSS0_CORE0_INTR_IN_251 | 251 | MCASP4_XMIT_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_252 | 252 | MCASP4_REC_INTR_PEND_0 |
R5FSS0_CORE0_INTR_IN_254 | 254 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_26 |
R5FSS0_CORE0_INTR_IN_255 | 255 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_27 |