Integrated in MAIN domain: One
instance of the Peripheral Component Interconnect express (PCIe) subsystem module
with shared SerDes lines, provides the following main features:
- Compliant to PCI-Express® Base Specification, Revision 4.0 (Version
0.7)
- 1-lane configuration with up to 8.0
Gbps/lane (Gen3).
- Gen3 (8 Gbps 128/130-bit encoding),
Gen2 (5 Gbps 8/10-bit encoding), and Gen1 (2.5 Gbps 8/10-bit encoding) with
auto-negotiation
- Dual mode: Root Port (RP) or
End Point (EP) operation modes, selectable via bootstrap pins
- Dynamic PIPE width change
when switching between Gen1/2/3 modes
- Constant 32-bit PIPE width
for Gen1/2/3 modes
- Maximum payload size of 128 bytes
- Maximum remote read request
size of 4KB
- Dual mode: Root Port (RP) or
End Point (EP) operation modes
- Maximum number of non-posted
outstanding transactions: 32
- Resizable Base Address
Registers (BAR) capability
- Separate Reference Clock with
Independent Spread (SRIS)
- Legacy, MSI and MSI-X
Interrupt Support
- 32 outbound address
translation regions
- Precision time measurement
(PTM)