If a user does not want to use the Vector Address registers, the VIM may be used as a
more traditional interrupt controller. Note that in this mode, there is no hardware
priority masking (because the FIQ Vector Address (Base Address + 0x1C) is never
read). Software would be responsible for doing all priority operations
- Determine which interrupt to service
- Read the Prioritized FIQ (Base Address + 0x0C) to determine which
interrupt is the highest priority FIQ currently asserted OR
- Optionally read the FIQ Group Status (Base Address + 0x14) to
determine which groups have IRQs pending, then read the Group
M Interrupt FIQ Enabled Status/Clear Register (Base
Address + 0x400 + M*0x20 + 0x14) and use a software
prioritization scheme to determine which FIQ to service
- Service the interrupt
- Depending on whether the original source of the interrupt was a pulse or a
level (Determined by reading the Group M Type Map Register (Base
Address + 0x200 + M*0x20 + 0x1C) to determine type)
- Pulse
- Clear the status by writing a 1 to the appropriate bit in
the Group M Interrupt Enabled Status/Clear Register
(Base Address + 0x400 + M*0x20 + 0x04) or Group
M Interrupt FIQ Enabled Status/Clear Register
(Base Address + 0x400 + M*0x20 + 0x14)
- Clear the interrupt at the source
- This way, the source can generate another pulse if
it needs to and the VIM will process this as a new
interrupt
- Level
- Clear the interrupt at the source
- Clear the status by writing a 1 to the appropriate bit in
the Group M Interrupt Enabled Status/Clear Register
(Base Address + 0x400 + M*0x20 + 0x04) or Group
M Interrupt FIQ Enabled Status/Clear Register
(Base Address + 0x400 + M*0x20 + 0x14)
- This way, the level should be gone at the input to
the VIM, it will avoid falsely re-calling the
interrupt
- If the source maintains the level, then it means
there is another interrupt