The PCIe subsystem does not support
the following features:
- PCIe beacon for in-band wake
- Vendor Messaging
- I/O access in inbound direction in
RC
or EP mode
- Addressing modes other than incremental for burst transactions.
As a result, the PCIe addresses cannot be in cacheable memory space.
- Single-root I/O virtualization (SR-IOV)
- Address Translation Services (ATS) capability to support
virtualization in
RC
mode
- L2 power state
- PCI Device Power Management state D3Cold
- Hot-plug
- 48-bit address on VBUSM controller and target interfaces. Only
36-bit address is supported for these interfaces.
- Parity checking on VBUSM and VBUSP interfaces