SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The procedure in Table 12-284 configures the receive clock generator of the MCASP module.
The settings in below table Table 12-284 have no effect, if MCASP_ACLKXCTL[6] ASYNC = 0 (this is, receive clock is sourced from the inverted version of the transmit clock). For example, such is the case when MCASP loopback mode is used.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
To use the MCASP receive clock generator, select an asynchronous receiver clock schema (ASYNC = 1). Otherwise an inverted version of transmit clock XCLK is used (receiver synchronized with transmitter). | MCASP_ACLKXCTL[6] ASYNC | 0b1 |
IF receive clock - RCLK is internally generated | Software test condition | |
The high-speed receive clock - AHCLKR is internally generated based on AUXCLK | ||
Select an internally-generated high-frequency clock. | MCASP_AHCLKXCTL[15] HCLKRM | 0b1 |
Select the internal high-speed clock source polarity: non-inverted or inverted. | MCASP_AHCLKXCTL[14] HCLKRP | 0x- |
Set the divisor for the internally generated high-frequency clock – AHCLKR in range (1 - 4096). | MCASP_AHCLKXCTL[11-0] HCLKRDIV | 0x- |
Select an internally-generated receive clock. | MCASP_ACLKXCTL[5] CLKRM | 0b1 |
Receiver samples on rising/falling edge. Select Rx sampling on the rising edge if transmitter shifts out on falling edge, and vice versa. | MCASP_ACLKXCTL[7] CLKRP | 0x- |
Set the divisor for the internally generated receive clock– ACLKR in range (1 - 32). | MCASP_ACLKXCTL[4-0] CLKRDIV | 0x- |
Optional: If MCASP receiver is required to output internally generated clock, ACLKR pin must be set as an output in step 9 of the sequence documented in the Table 12-281. This must not be done in current step because the clock control register - MCASP_ACLKRCTL must be appropriately configured prior to ACLKR pin outputting a receive clock to an external device. | MCASP_PDIR[29] ACLKR | 0b1 |
ELSE | ||
Select an externally-generated receive clock. Note that in this case the AHCLKR signal path and the CLKRDIV divider are NOT used. | MCASP_ACLKXCTL[5] CLKRM | 0b0 |
Receiver samples on rising/falling edge. Select Rx sampling on the rising edge if transmitter shifts out on falling edge, and vice versa. | MCASP_ACLKXCTL[7] CLKRP | 0x- |
Setup an input direction for the ACLKR pin | MCASP_PDIR[29] ACLKR | 0b0 |
ENDIF | ||
Configure the transmit clock failure detect logic. | See Section 12.5.2.4.15.6.1, Clock Failure Check Startup. |