SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The VBUSM2AXI bridge implements a 64-line deep ECC cache for improving inline ECC performance. Each cache line can be allocated to an initiator in the system based on its Route ID. The Route ID allocation to cache line can be done by writing to the EMIF_SSCFG_ECC_RID_INDX_REG and EMIF_SSCFG_ECC_RID_VAL_REG registers. Since the bridge uses unallocated cache lines for all read accesses without Route ID allocation, one or more locations in the cache should be kept unallocated for better performance. To ensure that at least one cache line remains unallocated, in the case all cache lines are allocated by software, the bridge automatically unallocates the 63rd cache line. Write accesses without Route ID allocation result in ECC and data writes to the SDRAM, when the EMIF_SSCFG_ECC_CTRL_REG[4] WR_ALLOC bit is set to 0x0. When EMIF_SSCFG_ECC_CTRL_REG[4] WR_ALLOC is set to 0x1, an unassigned cache-line is allocated to write accesses without Route ID allocation.