A53SS0 |
A53SS0_cnthpirq0_0 |
GICSS0_ppi0_0_IN_26 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cnthpirq1_0 |
GICSS0_ppi0_1_IN_26 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cnthpirq2_0 |
GICSS0_ppi0_2_IN_26 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cnthpirq3_0 |
GICSS0_ppi0_3_IN_26 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpnsirq0_0 |
GICSS0_ppi0_0_IN_30 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpnsirq1_0 |
GICSS0_ppi0_1_IN_30 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpnsirq2_0 |
GICSS0_ppi0_2_IN_30 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpnsirq3_0 |
GICSS0_ppi0_3_IN_30 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpsirq0_0 |
GICSS0_ppi0_0_IN_29 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpsirq1_0 |
GICSS0_ppi0_1_IN_29 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpsirq2_0 |
GICSS0_ppi0_2_IN_29 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntpsirq3_0 |
GICSS0_ppi0_3_IN_29 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntvirq0_0 |
GICSS0_ppi0_0_IN_27 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntvirq1_0 |
GICSS0_ppi0_1_IN_27 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntvirq2_0 |
GICSS0_ppi0_2_IN_27 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_cntvirq3_0 |
GICSS0_ppi0_3_IN_27 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_commirq0_0 |
GICSS0_ppi0_0_IN_22 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_commirq1_0 |
GICSS0_ppi0_1_IN_22 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_commirq2_0 |
GICSS0_ppi0_2_IN_22 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_commirq3_0 |
GICSS0_ppi0_3_IN_22 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq0_0 |
GICSS0_ppi0_0_IN_24 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq0_0 |
GICSS0_ppi0_1_IN_17 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq0_0 |
GICSS0_ppi0_2_IN_17 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq0_0 |
GICSS0_ppi0_3_IN_17 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq1_0 |
GICSS0_ppi0_0_IN_18 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq1_0 |
GICSS0_ppi0_1_IN_24 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq1_0 |
GICSS0_ppi0_2_IN_18 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq1_0 |
GICSS0_ppi0_3_IN_18 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq2_0 |
GICSS0_ppi0_0_IN_19 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq2_0 |
GICSS0_ppi0_1_IN_19 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq2_0 |
GICSS0_ppi0_2_IN_24 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq2_0 |
GICSS0_ppi0_3_IN_19 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq3_0 |
GICSS0_ppi0_0_IN_20 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq3_0 |
GICSS0_ppi0_1_IN_20 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq3_0 |
GICSS0_ppi0_2_IN_20 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ctiirq3_0 |
GICSS0_ppi0_3_IN_24 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr0_corrected_err_level_0 |
ESM0_esm_lvl_event_IN_24 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr0_uncorrected_err_level_0 |
ESM0_esm_lvl_event_IN_94 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr1_corrected_err_level_0 |
ESM0_esm_lvl_event_IN_25 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr1_uncorrected_err_level_0 |
ESM0_esm_lvl_event_IN_93 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr2_corrected_err_level_0 |
ESM0_esm_lvl_event_IN_45 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr2_uncorrected_err_level_0 |
ESM0_esm_lvl_event_IN_46 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr3_corrected_err_level_0 |
ESM0_esm_lvl_event_IN_47 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr3_uncorrected_err_level_0 |
ESM0_esm_lvl_event_IN_48 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr_corepac_corrected_err_level_0 |
ESM0_esm_lvl_event_IN_26 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_ecc_eccaggr_corepac_uncorrected_err_level_0 |
ESM0_esm_lvl_event_IN_95 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_exterrirq_0 |
ESM0_esm_lvl_event_IN_144 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_interrirq_0 |
ESM0_esm_lvl_event_IN_145 |
ESM0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_pmuirq0_0 |
GICSS0_ppi0_0_IN_23 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_pmuirq1_0 |
GICSS0_ppi0_1_IN_23 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_pmuirq2_0 |
GICSS0_ppi0_2_IN_23 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_pmuirq3_0 |
GICSS0_ppi0_3_IN_23 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_vcpumntirq0_0 |
GICSS0_ppi0_0_IN_25 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_vcpumntirq1_0 |
GICSS0_ppi0_1_IN_25 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_vcpumntirq2_0 |
GICSS0_ppi0_2_IN_25 |
GICSS0 |
A53SS0 interrupt request |
level |
A53SS0 |
A53SS0_vcpumntirq3_0 |
GICSS0_ppi0_3_IN_25 |
GICSS0 |
A53SS0 interrupt request |
level |