SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The RTC can produce one HW event output active high level and active high pulse. This one output will assert on 3 internal HW events.
HOST PROCESSOR can read the Interrupt MMR status to determine which events caused the RTC event output to assert. vbus_clk can be on or off, the active high level will assert on either scenario. The 32768Hz clock must be active to cause a ON_OFF or OFF_ON event. The External Wakeup event can occur without 32768Hz clock if debounce is not enabled.
The Interrupt MMR programing model uses the standard Keystone3 schema which allows HOST PROCESSOR to issue debug event. Also, the enabling of the events are backed up in the ON domain, so HOST PROCESSOR will not enable to enable events on every power cycle of the CORE domain.