SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
A prescaler can be used to divide the timer counter input clock frequency. The prescaler is enabled when the DMTIMER1MS_TCLR[5] PRE bit is set. The DMTIMER1MS_TCLR[4-2] PTV bit field sets the 2n division ratio (prescaler value is 2(PTV + 1). The prescaler counter is reset when the timer counter is stopped or reloaded on-the-fly.
Table 12-328 lists the prescaler/timer reload values versus contexts.
Context | Prescaler | Timer Counter |
---|---|---|
Overflow (when autoreload is on) | Reset | DMTIMER1MS_TLDR[31-0] |
DMTIMER1MS_TCRR write | Reset | DMTIMER1MS_TCRR[31-0] |
DMTIMER1MS_TTGR write | Reset | DMTIMER1MS_TLDR[31-0] |
Stop | Reset | Frozen |