SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The VPAC subsystem outputs six physical system interrupt lines: VPAC_LEVEL_0_INTR through VPAC_LEVEL_5_INTR. For more information on how the interrupt lines are connected at SoC level, see VPAC Integration. The interrupt aggregation within the VPAC subsystem is done using the internal INTD module. Each interrupt line can be mapped to the same list of source interrupt events generated by the modules within the VPAC subsystem.
Table 7-77 shows the INTD interrupt control registers for each VPAC interrupt line. Each interrupt line has a separate set of registers for level and pulse input event types. Each bit in a register corresponds to a particular interrupt event. For more details on the mapping of interrupt events to INTD register bits, see Table-XXX further below.
Output System Interrupt Line | Input Interrupt Event Type | Interrupt Enable Registers | Interrupt Clear Registers | Interrupt Status Registers | Interrupt Status Clear Registers |
---|---|---|---|---|---|
VPAC_LEVEL_0_INTR | Level | VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_0 through VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_7 | VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_0_0 through VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_0_7 | VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_0 through VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_7 |
Pulse | VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_0_0 through VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_0_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_7 | VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_0_0 through VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_0_7 | VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_0_0 through VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_0_7 | |
VPAC_LEVEL_1_INTR | Level | VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_0 through VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_7 | VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_1_0 through VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_1_7 | VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_0 through VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_7 |
Pulse | VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_1_0 through VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_1_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_7 | VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_1_0 through VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_1_7 | VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_1_0 through VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_1_7 | |
VPAC_LEVEL_2_INTR | Level | VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_0 through VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_7 | VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_2_0 through VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_2_7 | VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_0 through VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_7 |
Pulse | VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_2_0 through VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_2_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_7 | VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_2_0 through VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_2_7 | VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_2_0 through VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_2_7 | |
VPAC_LEVEL_3_INTR | Level | VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_3_0 through VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_3_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_7 | VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_3_0 through VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_3_7 | VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_0 through VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_7 |
Pulse | VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_3_0 through VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_3_7 | PAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_7 | VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_3_0 through VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_3_7 | VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_3_0 through VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_3_7 | |
VPAC_LEVEL_4_INTR | Level | VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_0 through VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_7 | VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_4_0 through VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_4_7 | VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_0 through VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_7 |
Pulse | VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_4_0 through VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_4_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_7 | VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_4_0 through VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_4_7 | VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_4_0 through VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_4_7 | |
VPAC_LEVEL_5_INTR | Level | VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_5_0 through VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_5_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_7 | VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_5_0 through VPAC_INTD_CFG_STATUS_REG_LEVEL_VPAC_OUT_5_7 | VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_0 through VPAC_INTD_CFG_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_7 |
Pulse | VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_5_0 through VPAC_INTD_CFG_ENABLE_REG_PULSE_VPAC_OUT_5_7 | VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_0 through VPAC_INTD_CFG_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_7 | VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_5_0 through VPAC_INTD_CFG_STATUS_REG_PULSE_VPAC_OUT_5_7 | VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_5_0 through VPAC_INTD_CFG_STATUS_CLR_REG_PULSE_VPAC_OUT_5_7 |
The VISS interrupt events are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_0 through VPAC_INTD_xxx_VPAC_OUT_5_0 registers. Table 7-78 provides more details on the VISS interrupt events. All VISS interrupts are single pulse event signals.
Register Bit | Interrupt Event Name | Description |
---|---|---|
0 | RAWFE_CFG_ERR_INTR | Config read or write memory acccess occurred during functional operation and likely corrupted functional opertion. VISS merges all config error sources from RawFE and refer to RawFE spec for the entire error source list. |
1 | RAWFE_AEW_PULSE_INTR | H3A AEW interrupt. |
2 | RAWFE_AF_PULSE_INTR | H3A AF interrupt. |
3 | RAWFE_H3A_PULSE_INTR | H3A interrupt. |
4 | RAWFE_H3A_BUF_OVRFLOW_PULSE_INTR | H3A output buffer overflow. |
5 | NSF4V_LINEMEM_CFG_ERR_INTR | VBUSP diagnostic read access of RAM, while NSF data using RAM for functional
purpose. |
6 | NSF4V_HBLANK_ERR_INTR | Horzontal Blanking too short between lines. |
7 | NSF4V_VBLANK_ERR_INTR | Vertical Blanking too short between frames. |
8 | GLBCE_CFG_ERR_INTR | Either non-shadowed registers written or statastic memories are accessed during active window. |
9 | GLBCE_FILT_START_INTR | GLBCE started filtering. This interrupt is issued at the rising edge of filtering signal. |
10 | GLBCE_FILT_DONE_INTR | GLBCE ended filtering. This interrupt is issued at the falling edge of filtering signal. |
11 | GLBCE_HSYNC_ERR_INTR | Generated when delayed HS/HE signals doesn’t match with derived signals from GLBCE core. |
12 | GLBCE_VSYNC_ERR_INTR | Generated when delayed VS/VE signals doesn’t match with derived signals from GLBCE core. |
13 | GLBCE_VP_ERR_INTR | This interrupt is issued, if there is a data input while filtering is high. |
14 | FCFA_CFG_ERR_INTR | Either non-shadowed registers written or line memories are accessed during active window. |
15 | FCC_CFG_ERR_INTR | Configuration access to registers/memories has corrupted functional operation. |
Configuration read or write memory acccess occurred during functional operation. | ||
Merged independent error sources at VISS. Refer to Section VISS Flexible Color Processing (FCP) for all sources. | ||
16 | FCC_OUTIF_OVF_ERR_INTR | FIFO overflow on FIFO for Y12 LSE I/F. Merged all FCC output overflow error sources at VISS. Refer to Section VISS Flexible Color Processing (FCP) for all sources. |
17 | FCC_HIST_READ_ERR_INTR | Host was not able to read the entire histogram mem between VS-VE window (triggered when the first access to histogram has been performed but the last has not been performed). |
18 | EE_CFG_ERR | Cinfiguration happened to EE regions causing corruption during frame processing. |
19 | EE_SYNCOVF_ERR | EE horizontal synchronization FIFO overflow interrupt. |
20 | LSE_FR_DONE_EVT_INTR | LSE frame done interrupt. |
21 | LSE_SL2_RD_ERR_INTR | Set whenever there is an error response on VBUSM read command for any input channel. |
22 | LSE_SL2_WR_ERR_INTR | Set whenever there is an error response on VBUSM write command for any output channel. |
23 | LSE_CAL_VP_ERR_INTR | Set whenever one of the following input frame errors is detected at VPORT_INPUT. |
24 | LSE_OUT_FR_START_EVT_INTR | Ouput Frame Start (from VISS top level). |
The LDC interrupt events are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_1 through VPAC_INTD_xxx_VPAC_OUT_5_1 registers. Table 7-79 provides more details on the LDC interrupt events. All LDC interrupts are single pulse event signals.
Register Bit | Interrupt Event Name | Description |
---|---|---|
0 | LDC_PIX_IBLK_OUTOFBOUND_INTR | Back mapped pixel co-ordinate goes out of the pre-computed input pixel bounding box. |
1 | LDC_MESH_IBLK_OUTOFBOUND_INTR | Block mesh co-ordinate goes out of the pre-computed mesh bounding box. |
2 | LDC_PIX_IBLK_MEMOVF_INTR | Input Pixel block memory overflow. |
3 | LDC_MESH_IBLK_MEMOVF_INTR | Mesh block memory overflow. |
4 | LDC_IFR_OUTOFBOUND_INTR | Back mapped input co-ordinate goes out of input frame range. |
5 | LDC_INT_SZOVF_INTR | Affine and perspective transform precision overflow error. |
6 | LDC_FR_DONE_EVT_INTR | Frame done LDC. |
7 | LDC_SL2_WR_ERR_INTR | Error on SL2 VBSUM Write interface. |
8 | LDC_VBUSM_RD_ERR_INTR | Error on Input VBUSM Read interface. |
The MSC interrupt events are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_2 through VPAC_INTD_xxx_VPAC_OUT_5_2 registers. Table 7-80 provides more details on the MSC interrupt events. All MSC interrupts are single pulse event signals.
Register Bit | Interrupt Event Name | Description |
---|---|---|
0 | MSC_LSE_FR_DONE_EVT_0_INTR | Frame done MSC processing thread 0. |
1 | MSC_LSE_FR_DONE_EVT_1_INTR | Frame done MSC processing thread 1. |
2 | MSC_LSE_SL2_RD_ERR_INTR | Error on SL2 VBSUM Read interface. |
3 | MSC_LSE_SL2_WR_ERR_INTR | Error on SL2 VBSUM Write interface. |
The NF interrupt events are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_2 through VPAC_INTD_xxx_VPAC_OUT_5_2 registers. Table 7-81 provides more details on the NF interrupt events. All NF interrupts are single pulse event signals.
Register Bit | Interrupt Event Name | Description |
---|---|---|
8 | NF_FR_DONE_INTR | Frame done NF. |
9 | NF_SL2_WR_ERR_INTR | Error on SL2 VBSUM Write interface. |
10 | NF_SL2_RD_ERR_INTR | Error on SL2 VBSUM Read interface. |
The HTS interrupt events are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_3 through VPAC_INTD_xxx_VPAC_OUT_5_3 registers. Table 7-82 provides more details on the HTS interrupt events. All HTS interrupts are single pulse event signals, save for the SPARE_PEND_xxx interrupts, which can be both single pulse events and level events.
Register Bit | Interrupt Event Name | Description |
---|---|---|
0 | PIPE_DONE_0 | Pipeline 0 done. |
1 | PIPE_DONE_1 | Pipeline 1 done. |
2 | PIPE_DONE_2 | Pipeline 2 done. |
3 | PIPE_DONE_3 | Pipeline 3 done. |
4 | PIPE_DONE_4 | Pipeline 4 done. |
5 | PIPE_DONE_5 | Pipeline 5 done. |
6 | PIPE_DONE_6 | Pipeline 6 done. |
7 | TDONE | HWA0 thread done. |
8 | RESERVED | Reserved. |
9 | TDONE | HWA2 thread done. |
10 | RESERVED | Reserved. |
11 | TDONE | HWA4 thread done. |
12 | TDONE | HWA5 thread done. |
13 | TDONE | HWA6 thread done. |
14 | SPARE_DEC_0 | Spare 0 scheduler decrement pulse (ehost mode). |
15 | SPARE_DEC_1 | Spare 1 scheduler decrement pulse (ehost mode). |
16 | SPARE_PEND_0_PULSE | Spare 0 scheduler pend assertion (ehost mode). |
17 | SPARE_PEND_0_LEVEL | Spare 0 scheduler pend assertion (ehost mode). |
18 | SPARE_PEND_1_PULSE | Spare 1 scheduler pend assertion (ehost mode). |
19 | SPARE_PEND_1_LEVEL | Spare 1 scheduler pend assertion (ehost mode). |
20 | WATCHDOGTIMER_ERR_0 | Watchdog Timeout Error for HWA0. |
21 | RESERVED | Reserved. |
22 | WATCHDOGTIMER_ERR_2 | Watchdog Timeout Error for HWA2. |
23 | RESERVED | Reserved. |
24 | WATCHDOGTIMER_ERR_4 | Watchdog Timeout Error for HWA4. |
25 | WATCHDOGTIMER_ERR_5 | Watchdog Timeout Error for HWA5. |
26 | WATCHDOGTIMER_ERR_6 | Watchdog Timeout Error for HWA6. |
The UTC interrupt events indicating TR complete are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_4 through VPAC_INTD_xxx_VPAC_OUT_5_4 registers for UTC0, and VPAC_INTD_xxx_VPAC_OUT_0_5 through VPAC_INTD_xxx_VPAC_OUT_5_5 plus VPAC_INTD_xxx_VPAC_OUT_0_6 through VPAC_INTD_xxx_VPAC_OUT_5_6 registers for UTC1. Table 7-83 provides more details on the UTC TR complete interrupt events. All UTC TR complete interrupts are single pulse event signals.
Register Bit | Interrupt Event Name | Description |
---|---|---|
31-0 | UTC0_COMPLETE_INTR[31:0] | TR complete interrupt. |
31-0 plus 31-0 | UTC1_COMPLETE_INTR[63:0] | TR complete interrupt. |
The UTC interrupt events indicating error are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_7 through VPAC_INTD_xxx_VPAC_OUT_5_7 registers for both UTC0 and UTC1. Table 7-84 provides more details on the UTC error interrupt events. All UTC error interrupts are single pulse event signals.
Register Bit | Interrupt Event Name | Description |
---|---|---|
0 | UTC0_ERR | UTC0 error. |
1 | UTC1_ERR | UTC1 error. |
2 | UTC0_PROT_ERR_INTR | UTC0 protocol violation. |
3 | UTC1_PROT_ERR_INTR | UTC1 protocol violation. |
The CTSET interrupt events are mapped to register bits within the VPAC_INTD_xxx_VPAC_OUT_0_7 through VPAC_INTD_xxx_VPAC_OUT_5_7 registers. Table 7-85 provides more details on the CTSET events. All CTSET error interrupts are single pulse event signals.
Register Bit | Interrupt Event Name | Description |
---|---|---|
4 | CTM_PULSE_INTR | Counter Timer Module (CTM) pulse interrupt. |