SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Each MCSPI channel, if enabled, can issue DMA requests. There are two DMA request lines per MCSPI channel (one for read and one for write).
The DMA read request line is asserted when the MCSPI channel is enabled and new data is available in the receive register of the MCSPI channel. A DMA read request can be individually masked with the MCSPI_CHiCONF[15] DMAR bit. The DMA read request line is de-asserted when reading of the MCSPI_RXi register of the MCSPI channel completes.
The DMA write request line is asserted when the MCSPI channel is enabled and the MCSPI_TXi register of the MCSPI channel is empty. A DMA write request can be individually masked with the MCSPI_CHiCONF[14] DMAW bit. The DMA write request line is de-asserted when loading of the MCSPI_TXi register of the channel completes.