The GICSS has the following main interfaces:
- A pair of 64-bit VBUSM write-only and read-only
controller interfaces
- AXI2VBUSM bridge converts
the standard 64-bit AXI4 controller interface into this pair of
interfaces
- The AXI4 controller
interface allows the GICSS ITS and redistributors to access main
memory
- 32-bit VBUSM peripheral interface
- Provides access to Arm
GIC-500 internal resources
- Handles all message-based
interrupts. Message-based interrupts can generate SPIs or LPIs,
depending on the register that is written
- VBUSM2AXI bridge converts
this interface into an 32-bit AXI4 peripheral interface
- 32-bit VBUSP peripheral interface
- Provides access to
internal ECC aggregator
- Physical interrupt and power signals
- Inputs: CPU active signals, SPIs and PPIs (can be programmed as either level-sensitive, or edge-triggered)
- Outputs: Error signals and wake-up requests
- GIC Stream Protocol Interface
- Consists of a pair of AXI4-Stream interfaces (one upstream and one downstream 16-bit AXI4-Stream interface) that the GICSS uses to send interrupts to the core and receive notifications when the core activates interrupts
- There is a pair of physical interfaces, one in each direction, for each cluster