SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
DISPC includes two input pipelines:
The video pipeline (VID) consists of:
The video lite pipeline (VIDL1) is identical to the video pipeline (VID), except for:
Each pipeline processing block can be independently bypassed.
The input of each pipeline is connected to the video DMA buffer controller. Each pipeline pixel output is always connected to the overlay managers (OVR1 and OVR2). Each pipeline configuration supports various BITMAP, RGB (ARGB and RGBA), and YUV formats, as listed in Table 12-427, DISPC Pixel Data Formats.
The 256-entry CLUT is either used to convert BITMAP (1, 2, 4, or 8-bit indexed formats) into RGB format, or for RGB to RGB inverse gamma correction. For a BITMAP format data, scaling is not supported. Scaling and color look-up table features are mutually exclusive. If the color look-up feature is enabled, then video pipeline scaler has to be disabled.
For chroma sub-sampled YUV formats (YUV422 and YUV420-NV12/NV21):
For ARGB source data with less than/equal to 10-bit component data size the replication logic (ARGB expansion) converts the data to ARGB48 by replicating the MSBs into the LSBs:
A pipeline can be enabled by setting the DSS0_VID_ATTRIBUTES[0] ENABLE register bit. If the video pipeline is disabled, the video window does not exist on the screen and the whole video pipeline and its DMA are inactive. Prior to enabling the video layer a valid configuration has to be set by the user.
The DISPC input pipelines, VID and VID1L, will be commonly referred to as video pipeline (VID) in the following sections. Any differences in their functionality will be highlighted.