SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The Arm A53 Cluster natively supports ECC/parity protection on A53 SRAMs and error injection on few memories. The A53SS adds error injection capability on all internal SRAM. This is a valuable TI addition to the Arm native implementation.
RAM | A53 Error Injection Support | TI Error Injection Support |
---|---|---|
L1 I-Cache Data | No | Single error injection |
L1 I-Cache Tag | No | Single error injection |
L1 D-Cache Data | Double error injection | Single and double error injection |
L1 D-Cache Tag | No | Single error injection |
L1 Data Dirty | No | Single error injection |
TLB RAM | No | Single error injection |
SCU Duplicate Tag | No | Single and double error injection |
L2 Tag RAM | Double error injection | Single and double error injection |
L2 Data RAM | Double error injection | Single and double error injection |
The ECC Aggregator for the cores stimulates errors in the following RAMs:
The ECC Aggregator for the L2 cache stimulates errors in the following RAMs: