Integrated
in the MAIN domain:One Data Movement subsystem named DMSS can be used for efficient
transfer of data support between software, firmware and hardware in all
combinations. It consists of the following main modules:
- Packet DMA Controller
- Block Copy DMA
Controller
- Ring Accelerator provides
hardware acceleration to enable straightforward passing of work between a
producer and a consumer and has the following main features:
- Supports
independent memory-mapped ring structures
- Supports various
modes for each ring based on usage and compatibility
- Provides single-word
deep shared incoming Transfer Response FIFO
- Provides bit-wide
source VBUSM read/write target interface for accesses from DMA
controller entities
- Secure proxy module is a
modified version of the proxy module and in addition has the following main
features:
- Provides proxy
function to store large data bursts that a host can only access in
smaller amounts
- Supports a
configurable number of threads, where each has their own independent
proxy function
- Keeps the large data
burst coherent until the complete data has been accessed
- Allows for
interleaved access between multiple hosts or tasks using multiple
proxy threads
- Supports a
configurable target resource. The target has a configurable number
of channels, size of each channel and base address
- Supports a
programmable fixed queue for each proxy thread
- Supports multiple
producers all writing to the same queue
- Supports programmable
thresholds for when to generate events
- Supports a max
message count for outbound proxy threads limiting the number of
messages a thread can produce
- Optionally supports
dynamic clock gating
- Interrupt Aggregator modules
provide a centralized machine which handles the termination of system events
to that they can be coherently processed by the host(s) in the system. Main
features are as follows:
- 64-bit VBUSP target using
64-bit registers
- Provide a set of TI
Interrupt Architecture compliant interrupt status and mask registers
which are used to pass specific event status to one or more host
blocks.
- Provides an optional
set of Unmapped event (UNMAP) which can take an 'unmapped' event
from the ingress ETL and generate a Global event on the egress Event
Transport Lane (ETL) interface.
- Provides an optional
set of Global Event Input (GEVI) counters which can count events
delivered via an ingress Event Transport Lane (ETL)
- Provides an optional
set of Local Event Input (LEVI) to Global event registers which can
be used to convert pulsed discrete interrupt inputs or clock
synchronous rising edge events into Global events on an egress
ETL
- Provides an optional
set of Global Event Input (GEVI) 'Multicast' registers which can
take a Global event from an ingress ETL and generate two egress
Global events on two egress ETL interfaces