SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The Fast-xSPI boot mode is an extension of the xSPI boot mode where the OSPI PHY will be tuned in order to set the frequency of operation to 100MHz for 8D-8D-8D mode. Flash needs to support SFDP.
To support Fast-xSPI boot, ROM expects the tuning configuration in the last sector of flash which is determined by the flash device configuration. Absence of the configuration will cause ROM to switch the non-PHY based/standard xSPI boot.
ROM will get the flash memory density (flash memory size S) andlargest erase sector size (E bytes) from the BFPT table and calculates the beginning of last sector as E bytes from the end of flash. We call this location as start of the configuration data (C0 = S - E)
Supported Configurations:
Selection between the two configurations is through magic words defined by ROM.
Offset from C0 | Bitfields | Description |
---|---|---|
0 to 127 | All | 128 byte calibration pattern |
128 to 131 | All |
4 byte Magic Word (defined by ROM). There are two distinct magic words to indicate
The magic word is stored in little endian format. Absence of the magic word leads the ROM use the non-PHY mode. |
132 to 135 | All |
4 byte unsigned int for clock frequency. Only 100Mhz is currently supported. ROM operates at 20 dummy cycles, so the flash should support the chosen frequency at 20 dummy cycles. The clock frequency is stored in little endian format. Any unknown clk freq leads ROM to the non-PHY mode. eg:
byte 132 - 00, 133 - E1, 134 - F5, 135 – 05 |
136 | 7:0 |
Flash Parameter Table version 0x00 or 0xFF - Parameter Table version 0 ( Not supported for Fast-xSPI boot) 0x01 - Parameter Table version 1 ( Latest version supported for Fast-xSPI boot) |
137 to 139 | All | 3 bytes are reserved must be set to 0xFF |
140 to 143 |
3 bytes for Tx_delay, Rx_delay, Rd_delay and one byte for padding. (Only used in case of offline tuning) Byte 143 - Padding must be set to 0xFF. |
|
144 to 158 |
15 parameters (one byte each) (Only used in case of online tuning) |
|
159 | 0 |
Determines if the master delay line locks on a full cycle or half cycle of delay. 0 - Full cycle of Delay 1 - Half cycle of Delay |
159 | 1 |
DLL bypass mode control Controls the bypass mode of the master and slave DLLs 0 - Master Operation mode 1 - Bypass mode |
159 | 4:2 |
DLL Phase Detect Selector for sampling clock generation to handle the clock domain crossing between the reference clock and sampling clock. Selects the number of delay elements to be inserted between the phase detect flip-flops: 3'b000 = One delay element 3'b001 = Two delay element 3'b010 = Three delay element 3'b011 = Four delay element 3'b100 = Five delay element 3'b101 = Six delay element 3'b110 = Seven delay element 3'b111 = Eight delay element |
159 | 7:5 | Reserved |
160 | 7:0 |
Secondary search offset: To ensure the search point is valid, we try to do a secondary search. Value provided in this field will be used as an offset which is added to the primary search point TxDLL and then Secondary search is performed from offseted TxDLL point. Supports value from 0 to 127 |
161 |
DLL Lock Timeout flag For non-zero flag value, calculated values of DllLockErrCnt and LoopbackLockErrCnt are ignored and 0 is returned instead. |
|
162 to 163 | DLL Lock Timeout value in µs. |
Parameters | Offset from C0 |
---|---|
Tx_delay | byte 140 |
Rx_delay | byte 141 |
Rd_delay | byte 142 |
0xFF (Padding) | byte 143 |
DLL Config parameter | byte 159 |
DLL lock timeout flag | byte 161 |
DLL lock timeout value in µs | byte 162 and 163 |
Parameters | Offset from C0 |
---|---|
Tx_Low_window_start | byte 144 |
Tx_Low_window_end | byte 145 |
Tx_High_window_start | byte 146 |
Tx_High_window_end | byte 147 |
Rx_min_bound_start | byte 148 |
Rx_min_bound_end | byte 149 |
Rx_max_bound_start | byte 150 |
Rx_max_bound_end | byte 151 |
Tx_min_bound_start | byte 152 |
Tx_min_bound_end | byte 153 |
Tx_max_bound_start | byte 154 |
Tx_max_bound_end | byte 155 |
Rd_Delay_init | byte 156 |
Rd_Delay_max | byte 157 |
Tx_offset_tuning_point | byte 158 |
DLL Config parameter | byte 159 |
Secondary Tx Search Offset | byte 160 |
DLL lock timeout flag | byte 161 |
DLL lock timeout value in µs | byte 162 and 163 |
The boot mode pin configuration and corresponding pin usage and mux configuration are shown below.
9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Rsvd (not for boot use) | OVRD | MCU Only | Primary Boot Mode A | PLL Config | |||||
X | X | X | X | 0 | 1 | 1 | X | X | X |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Backup Boot Mode Config | Primary Boot Mode Config | Backup Boot Mode | Primary Boot B | ||||
X | X | X | X | X | X | X | 1 |
Package Name | Function Name | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
---|---|---|---|---|---|---|---|
MCU_OSPI0_CLK | MCU_OSPI0_CLK | Disable | n/a | 0 | Disable | 0 | WKUP_PADCONFIG_0 |
MCU_OSPI0_LBCLKO | MCU_OSPI0_LBCLKO | Disable | n/a | 0 | Disable | 0 | WKUP_PADCONFIG_1 |
MCU_OSPI0_DQS | MCU_OSPI0_DQS | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_2 |
MCU_OSPI0_D0 | MCU_OSPI0_D0 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_3 |
MCU_OSPI0_D1 | MCU_OSPI0_D1 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_4 |
MCU_OSPI0_D2 | MCU_OSPI0_D2 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_5 |
MCU_OSPI0_D3 | MCU_OSPI0_D3 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_6 |
MCU_OSPI0_D4 | MCU_OSPI0_D4 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_7 |
MCU_OSPI0_D5 | MCU_OSPI0_D5 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_8 |
MCU_OSPI0_D6 | MCU_OSPI0_D6 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_9 |
MCU_OSPI0_D7 | MCU_OSPI0_D7 | Disable | n/a | 0 | Enable | 0 | WKUP_PADCONFIG_10 |
MCU_OSPI0_CSn0 | MCU_OSPI0_CSn0 | Disable | n/a | 0 | Disable | 0 | WKUP_PADCONFIG_11 |
MCU_OSPI0_CSn1 | MCU_OSPI0_CSn1 | Disable | n/a | 0 | Disable | 0 | WKUP_PADCONFIG_12 |