SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
There are no configuration fields for this boot mode. GPMC NOR boot only supports 16-bit non-mux memory.
Table 5-37 summarizes the GPMC pin configuration done by ROM code for GPMC NOR boot.
Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
---|---|---|---|---|---|---|---|
GPMC0_AD0 | GPMC0_AD0 | Disable | NA | 0 | Enable | 0 | PADCONFIG15 |
GPMC0_AD1 | GPMC0_AD1 | Disable | NA | 0 | Enable | 0 | PADCONFIG16 |
GPMC0_AD2 | GPMC0_AD2 | Disable | NA | 0 | Enable | 0 | PADCONFIG17 |
GPMC0_AD3 | GPMC0_AD3 | Disable | NA | 0 | Enable | 0 | PADCONFIG18 |
GPMC0_AD4 | GPMC0_AD4 | Disable | NA | 0 | Enable | 0 | PADCONFIG19 |
GPMC0_AD5 | GPMC0_AD5 | Disable | NA | 0 | Enable | 0 | PADCONFIG20 |
GPMC0_AD6 | GPMC0_AD6 | Disable | NA | 0 | Enable | 0 | PADCONFIG21 |
GPMC0_AD7 | GPMC0_AD7 | Disable | NA | 0 | Enable | 0 | PADCONFIG22 |
GPMC0_AD8 | GPMC0_AD8 | Disable | NA | 0 | Enable | 0 | PADCONFIG23 |
GPMC0_AD9 | GPMC0_AD9 | Disable | NA | 0 | Enable | 0 | PADCONFIG24 |
GPMC0_AD10 | GPMC0_AD10 | Disable | NA | 0 | Enable | 0 | PADCONFIG25 |
GPMC0_AD11 | GPMC0_AD11 | Disable | NA | 0 | Enable | 0 | PADCONFIG26 |
GPMC0_AD12 | GPMC0_AD12 | Disable | NA | 0 | Enable | 0 | PADCONFIG27 |
GPMC0_AD13 | GPMC0_AD13 | Disable | NA | 0 | Enable | 0 | PADCONFIG28 |
GPMC0_AD14 | GPMC0_AD14 | Disable | NA | 0 | Enable | 0 | PADCONFIG29 |
GPMC0_AD15 | GPMC0_AD15 | Disable | NA | 0 | Enable | 0 | PADCONFIG30 |
VOUT0_DATA0 | GPMC_A0 | Disable | NA | 0 | Disable | 1 | PADCONFIG46 |
VOUT0_DATA1 | GPMC_A1 | Disable | NA | 0 | Disable | 1 | PADCONFIG47 |
VOUT0_DATA2 | GPMC_A2 | Disable | NA | 0 | Disable | 1 | PADCONFIG48 |
VOUT0_DATA3 | GPMC_A3 | Disable | NA | 0 | Disable | 1 | PADCONFIG49 |
VOUT0_DATA4 | GPMC_A4 | Disable | NA | 0 | Disable | 1 | PADCONFIG50 |
VOUT0_DATA5 | GPMC_A5 | Disable | NA | 0 | Disable | 1 | PADCONFIG51 |
VOUT0_DATA6 | GPMC_A6 | Disable | NA | 0 | Disable | 1 | PADCONFIG52 |
VOUT0_DATA7 | GPMC_A7 | Disable | NA | 0 | Disable | 1 | PADCONFIG53 |
VOUT0_DATA8 | GPMC_A8 | Disable | NA | 0 | Disable | 1 | PADCONFIG54 |
VOUT0_DATA9 | GPMC_A9 | Disable | NA | 0 | Disable | 1 | PADCONFIG55 |
VOUT0_DATA10 | GPMC_A10 | Disable | NA | 0 | Disable | 1 | PADCONFIG56 |
VOUT0_DATA11 | GPMC_A11 | Disable | NA | 0 | Disable | 1 | PADCONFIG57 |
VOUT0_DATA12 | GPMC_A12 | Disable | NA | 0 | Disable | 1 | PADCONFIG58 |
VOUT0_DATA13 | GPMC_A13 | Disable | NA | 0 | Disable | 1 | PADCONFIG59 |
VOUT0_DATA14 | GPMC_A14 | Disable | NA | 0 | Disable | 1 | PADCONFIG60 |
VOUT0_DATA15 | GPMC_A15 | Disable | NA | 0 | Disable | 1 | PADCONFIG61 |
VOUT0_HSYNC | GPMC_A16 | Disable | NA | 0 | Disable | 1 | PADCONFIG62 |
VOUT0_DE | GPMC_A17 | Disable | NA | 0 | Disable | 1 | PADCONFIG63 |
VOUT0_VSYNC | GPMC_A18 | Disable | NA | 0 | Disable | 1 | PADCONFIG64 |
VOUT0_PCLK | GPMC_A19 | Disable | NA | 0 | Disable | 1 | PADCONFIG65 |
GPMC0_CSn3 | GPMC_A20 | Disable | NA | 0 | Disable | 2 | PADCONFIG45 |
GPMC0_ADVn_ALE | GPMC0_ADVn_ALE | Disable | NA | 0 | Disable | 0 | PADCONFIG33 |
GPMC0_OEn_REN | GPMC0_OEn_Ren | Disable | NA | 0 | Disable | 0 | PADCONFIG34 |
GPMC0_WEN | GPMC0_WEN | Disable | NA | 0 | Disable | 0 | PADCONFIG35 |
GPMC0_BE0n_CLE | GPMC0_BEOn_CLE | Disable | NA | 0 | Disable | 0 | PADCONFIG36 |
GPMC0_BE1n | GPMC0_BE1n | Disable | NA | 0 | Disable | 0 | PADCONFIG37 |
GPMC0_CSn0 | GPMC0_CSn0 | Disable | NA | 0 | Disable | 0 | PADCONFIG42 |
Only 21 address lines (GPMC0_A0 – GPMC0_A20) are used because the GPMC0_A21 and GPMC0_A22 lines are muxed with GPMC0_WAIT1 and GPMC0_WPn respectively.
GPMC0_A20 is muxed with GPMC0_CSn3, and ROM uses GPMC0_A20 for this address line. Thus, no CSn3 support when using GPMC NOR boot.
All signals in the table will be configured even though some may not be used by this particular boot mode.