When an FIQ interrupt is received, the CPU should follow these steps.
- Read the FIQ Vector Address (Base Address + 0x1C) and jump to that address to
service the ISR
- Reading this register will mask all interrupts of an equal or lower
priority and de-assert the FIQn output. If another interrupt of a higher
priority becomes available, the FIQn will re-assert, allowing priority
interruption of an interrupt.
- Reading this register will cause the value from the Prioritized FIQ
(Base Address + 0x0C) (which corresponds to the vector address) to be
loaded into the Active FIQ (Base Address + 0x24) and the valid bit to be
set
- Service the interrupt
- Depending on whether the original source of the interrupt was a pulse or a level
(Determined by reading the Active FIQ (Base Address + 0x24) to determine number
and reading the Group M Type Map Register (Base Address + 0x200 +
M*0x20 + 0x1C) to determine type)
- Pulse
- Clear the status by writing a 1 to the appropriate bit in the
Group M Interrupt Enabled Status/Clear Register (Base
Address + 0x400 + M*0x20 + 0x04) or Group M
Interrupt FIQ Enabled Status/Clear Register (Base Address +
0x400 + M*0x20 + 0x14)
- Clear the interrupt at the source
- This way, the source can generate another pulse if it
needs to and the VIM will process this as a new
interrupt
- Level
- Clear the interrupt at the source
- Clear the status by writing a 1 to the appropriate bit in the
Group M Interrupt Enabled Status/Clear Register (Base
Address + 0x400 + M*0x20 + 0x04) or Group M
Interrupt FIQ Enabled Status/Clear Register (Base Address +
0x400 + M*0x20 + 0x14)
- This way, the level should be gone at the input to the
VIM, it will avoid falsely re-calling the interrupt
- If the source maintains the level, then it means there
is another interrupt
- Write any value to the FIQ Vector Address (Base Address + 0x1C)
- This will clear the priority mask and all interrupts to be re-evaluated
for the new highest priority interrupt.
- This will clear the valid bit of the Active FIQ (Base Address +
0x24)