SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The event TXx_UNDERFLOW is activated when the channel is enabled and if the MCSPI_TXi register or the FIFO is empty (not updated with new data) when an external controller device starts a data transfer with the MCSPI (transmit and receive).
The TXi_UNDERFLOW is a harmless warning in controller mode.
To avoid having a TXi_UNDERFLOW event at the beginning of a transmission, the TXi_UNDERFLOW event is not activated when no data has been loaded into the MCSPI_TXi register, because the channel is enabled. To avoid having a TXx_UNDERFLOW event, the MCSPI_TXi register must seldom be loaded.
The MCSPI_IRQSTATUS TXi_UNDERFLOW interrupt status bit must be cleared for interrupt line deassertion (if the event is enabled as the interrupt source).