SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
An active low asynchronous hardware reset is provided to CSI_RX_IF by device LPSC. It is internally resynchronized to the functional clock domain.
A software reset is triggered by configuring the CSIRX_SOFT_RESET bit-fields for protocol reset and/or module reset.