SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Burst Event Mode uses the Short packet and Long packet structures to transmit the video information in short bursts and allow the system to use the Low Power states to save active power. This can only be supported with DSITX controllers able to store a horizontal line in the DPI FIFO. The burst mode will expect the tx_byte_clk to be twice the rate of the non burst event mode, and the register calculation will expect the total bytes for each line to double. Figure 12-562 illustrates the packet sequence for a single frame.
The DSITX controller registers for this mode are used to generate the exact number of bytes required for each horizontal line based on the DPI line configuration and the BPP for the colour pixel data.
The packet structure for each type of line during the frame is shown below, with the DSI HFP = 0 to select BLLP operation.
The DSI short packets and packet headers that are inserted by the controller for active lines must be accounted for:
Finally for lines with no active data, the controller will use either:
Program the DSI horizontal size registers as follows:
burst_mode = 1 and sync_pulse_active = sync_pulse_horizontal = 0;
Total Line Length = div_roundup((HLINE × bpp/8), num of lanes);
(BLKLINE_EVENT_PCK)} = (HLINE × bpp/8) × 2 - 4
(REG_LINE_DURATION)} = Total Line Length × 2 - div_roundup(4, number of lanes)
(VERT_BLANKING_DURATION)} = Total Line Length × 2 - div_roundup(4, number of lanes)
(BLKEOL_DURATION)} = Total Line Length × 2 - TX_BYTE_CYCLES
(BLKEOL_PCK) bytes} = Total Line Length × 2 - (HACT + HBP + HSS)
Note: TX_BYTE_CYCLES = TX Byte clock cycles to send Active Line bytes on the number of active lanes = div_roundup (HBP + HACT, number of lanes).
Burst Operation Frame Configuration
Burst mode operation can be used to save power provided the system configuration can support the higher tx_byte clock rate. The user should consider if the power saving during LP states is more than reducing the number of active lanes and running in non-burst mode.
The burst mode can only be used if the controller configuration can support it; either using SDI video interface, of DPI interface with a buffer size large enough to prefill the data. The video driver timing from the DPI side will also need to be changed.
For example:
The VESA configuration for a 1920x1200 frame at 60-frames per second with normal blanking would have a pixel clock at 193.25 MHz, HSA 200 pixels, HBP 336 pixels, HFP 136 pixels and total line 2592 pixels. This would need to be reconfigured to move the active area earlier in the horizontal line for the DSITX controller, so could be changed to; HSA 20 pixels, HBP 30 pixels, HFP 622 pixels. This would allow the HFP LP state to be almost ¼ of the line (622/2592).