RTI15 |
RTI15_intr_wwd_0 |
ESM0_esm_pls_event0_IN_248 |
ESM0 |
RTI15 interrupt request |
pulse |
RTI15 |
RTI15_intr_wwd_0 |
ESM0_esm_pls_event1_IN_248 |
ESM0 |
RTI15 interrupt request |
pulse |
RTI15 |
RTI15_intr_wwd_0 |
ESM0_esm_pls_event2_IN_248 |
ESM0 |
RTI15 interrupt request |
pulse |
RTI15 |
RTI15_intr_wwd_0 |
GICSS0_spi_IN_207 |
GICSS0 |
RTI15 interrupt request |
pulse |
RTI15 |
RTI15_intr_wwd_0 |
C7X256V0_CLEC_gic_spi_IN_207 |
C7X256V0_CLEC |
RTI15 interrupt request |
pulse |
RTI15 |
RTI15_intr_wwd_0 |
C7X256V1_CLEC_gic_spi_IN_207 |
C7X256V1_CLEC |
RTI15 interrupt request |
pulse |
RTI0 |
RTI0_intr_wwd_0 |
ESM0_esm_pls_event0_IN_224 |
ESM0 |
RTI0 interrupt request |
pulse |
RTI0 |
RTI0_intr_wwd_0 |
ESM0_esm_pls_event1_IN_224 |
ESM0 |
RTI0 interrupt request |
pulse |
RTI0 |
RTI0_intr_wwd_0 |
ESM0_esm_pls_event2_IN_224 |
ESM0 |
RTI0 interrupt request |
pulse |
RTI0 |
RTI0_intr_wwd_0 |
GICSS0_spi_IN_252 |
GICSS0 |
RTI0 interrupt request |
pulse |
RTI0 |
RTI0_intr_wwd_0 |
C7X256V0_CLEC_gic_spi_IN_252 |
C7X256V0_CLEC |
RTI0 interrupt request |
pulse |
RTI0 |
RTI0_intr_wwd_0 |
C7X256V1_CLEC_gic_spi_IN_252 |
C7X256V1_CLEC |
RTI0 interrupt request |
pulse |
RTI1 |
RTI1_intr_wwd_0 |
ESM0_esm_pls_event0_IN_225 |
ESM0 |
RTI1 interrupt request |
pulse |
RTI1 |
RTI1_intr_wwd_0 |
ESM0_esm_pls_event1_IN_225 |
ESM0 |
RTI1 interrupt request |
pulse |
RTI1 |
RTI1_intr_wwd_0 |
ESM0_esm_pls_event2_IN_225 |
ESM0 |
RTI1 interrupt request |
pulse |
RTI1 |
RTI1_intr_wwd_0 |
GICSS0_spi_IN_253 |
GICSS0 |
RTI1 interrupt request |
pulse |
RTI1 |
RTI1_intr_wwd_0 |
C7X256V0_CLEC_gic_spi_IN_253 |
C7X256V0_CLEC |
RTI1 interrupt request |
pulse |
RTI1 |
RTI1_intr_wwd_0 |
C7X256V1_CLEC_gic_spi_IN_253 |
C7X256V1_CLEC |
RTI1 interrupt request |
pulse |
RTI2 |
RTI2_intr_wwd_0 |
ESM0_esm_pls_event0_IN_241 |
ESM0 |
RTI2 interrupt request |
pulse |
RTI2 |
RTI2_intr_wwd_0 |
ESM0_esm_pls_event1_IN_241 |
ESM0 |
RTI2 interrupt request |
pulse |
RTI2 |
RTI2_intr_wwd_0 |
ESM0_esm_pls_event2_IN_241 |
ESM0 |
RTI2 interrupt request |
pulse |
RTI2 |
RTI2_intr_wwd_0 |
GICSS0_spi_IN_254 |
GICSS0 |
RTI2 interrupt request |
pulse |
RTI2 |
RTI2_intr_wwd_0 |
C7X256V0_CLEC_gic_spi_IN_254 |
C7X256V0_CLEC |
RTI2 interrupt request |
pulse |
RTI2 |
RTI2_intr_wwd_0 |
C7X256V1_CLEC_gic_spi_IN_254 |
C7X256V1_CLEC |
RTI2 interrupt request |
pulse |
RTI3 |
RTI3_intr_wwd_0 |
ESM0_esm_pls_event0_IN_242 |
ESM0 |
RTI3 interrupt request |
pulse |
RTI3 |
RTI3_intr_wwd_0 |
ESM0_esm_pls_event1_IN_242 |
ESM0 |
RTI3 interrupt request |
pulse |
RTI3 |
RTI3_intr_wwd_0 |
ESM0_esm_pls_event2_IN_242 |
ESM0 |
RTI3 interrupt request |
pulse |
RTI3 |
RTI3_intr_wwd_0 |
GICSS0_spi_IN_255 |
GICSS0 |
RTI3 interrupt request |
pulse |
RTI3 |
RTI3_intr_wwd_0 |
C7X256V0_CLEC_gic_spi_IN_255 |
C7X256V0_CLEC |
RTI3 interrupt request |
pulse |
RTI3 |
RTI3_intr_wwd_0 |
C7X256V1_CLEC_gic_spi_IN_255 |
C7X256V1_CLEC |
RTI3 interrupt request |
pulse |
RTI4 |
RTI4_intr_wwd_0 |
ESM0_esm_pls_event0_IN_236 |
ESM0 |
RTI4 interrupt request |
pulse |
RTI4 |
RTI4_intr_wwd_0 |
ESM0_esm_pls_event1_IN_236 |
ESM0 |
RTI4 interrupt request |
pulse |
RTI4 |
RTI4_intr_wwd_0 |
ESM0_esm_pls_event2_IN_236 |
ESM0 |
RTI4 interrupt request |
pulse |
RTI4 |
RTI4_intr_wwd_0 |
C7X256V0_CLEC_soc_events_in_IN_4 |
C7X256V0_CLEC |
RTI4 interrupt request |
pulse |
RTI5 |
RTI5_intr_wwd_0 |
ESM0_esm_pls_event0_IN_239 |
ESM0 |
RTI5 interrupt request |
pulse |
RTI5 |
RTI5_intr_wwd_0 |
ESM0_esm_pls_event1_IN_239 |
ESM0 |
RTI5 interrupt request |
pulse |
RTI5 |
RTI5_intr_wwd_0 |
ESM0_esm_pls_event2_IN_239 |
ESM0 |
RTI5 interrupt request |
pulse |
RTI5 |
RTI5_intr_wwd_0 |
C7X256V1_CLEC_soc_events_in_IN_4 |
C7X256V1_CLEC |
RTI5 interrupt request |
pulse |
RTI8 |
RTI8_intr_wwd_0 |
ESM0_esm_pls_event0_IN_249 |
ESM0 |
RTI8 interrupt request |
pulse |
RTI8 |
RTI8_intr_wwd_0 |
ESM0_esm_pls_event1_IN_249 |
ESM0 |
RTI8 interrupt request |
pulse |
RTI8 |
RTI8_intr_wwd_0 |
ESM0_esm_pls_event2_IN_249 |
ESM0 |
RTI8 interrupt request |
pulse |
RTI8 |
RTI8_intr_wwd_0 |
R5FSS0_CORE0_intr_IN_30 |
R5FSS0_CORE0 |
RTI8 interrupt request |
pulse |
MCU_RTI0 |
MCU_RTI0_intr_wwd_0 |
WKUP_ESM0_esm_pls_event0_IN_85 |
WKUP_ESM0 |
MCU_RTI0 interrupt request |
pulse |
MCU_RTI0 |
MCU_RTI0_intr_wwd_0 |
WKUP_ESM0_esm_pls_event1_IN_85 |
WKUP_ESM0 |
MCU_RTI0 interrupt request |
pulse |
MCU_RTI0 |
MCU_RTI0_intr_wwd_0 |
WKUP_ESM0_esm_pls_event2_IN_85 |
WKUP_ESM0 |
MCU_RTI0 interrupt request |
pulse |
MCU_RTI0 |
MCU_RTI0_intr_wwd_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_30 |
MCU_R5FSS0_CORE0 |
MCU_RTI0 interrupt request |
pulse |
WKUP_RTI0 |
WKUP_RTI0_intr_wwd_0 |
WKUP_ESM0_esm_pls_event0_IN_86 |
WKUP_ESM0 |
WKUP_RTI0 interrupt request |
pulse |
WKUP_RTI0 |
WKUP_RTI0_intr_wwd_0 |
WKUP_ESM0_esm_pls_event1_IN_86 |
WKUP_ESM0 |
WKUP_RTI0 interrupt request |
pulse |
WKUP_RTI0 |
WKUP_RTI0_intr_wwd_0 |
WKUP_ESM0_esm_pls_event2_IN_86 |
WKUP_ESM0 |
WKUP_RTI0 interrupt request |
pulse |
WKUP_RTI0 |
WKUP_RTI0_intr_wwd_0 |
ESM0_esm_pls_event0_IN_227 |
ESM0 |
WKUP_RTI0 interrupt request |
pulse |
WKUP_RTI0 |
WKUP_RTI0_intr_wwd_0 |
ESM0_esm_pls_event1_IN_227 |
ESM0 |
WKUP_RTI0 interrupt request |
pulse |
WKUP_RTI0 |
WKUP_RTI0_intr_wwd_0 |
ESM0_esm_pls_event2_IN_227 |
ESM0 |
WKUP_RTI0 interrupt request |
pulse |
WKUP_RTI0 |
WKUP_RTI0_intr_wwd_0 |
WKUP_R5FSS0_CORE0_intr_IN_30 |
WKUP_R5FSS0_CORE0 |
WKUP_RTI0 interrupt request |
pulse |