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微控制器 (MCU) 與處理器
微處理器和 DSP
汽車駕駛輔助 SoC

TDA2HG

現行

適用於 ADAS 應用且具圖形、視訊與視覺加速功能的 SoC 處理器

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產品規格表
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TDA2HG

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A15 Frequency (MHz) 500, 750 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators Embedded vision engines, Image video accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 1 Arm Cortex-A15 Frequency (MHz) 500, 750 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators Embedded vision engines, Image video accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ABC) 760 529 mm² 23 x 23
  • Architecture designed for ADAS applications
  • Video, image, and gaphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Orocessing Units (IPU)
  • Vision acceleration pac
    • Up to four Embedded Vision Engines (EVEs)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • 2-port gigabit ethernet (GMAC)
  • Enhanced Direct Memory Access (EDMA) controller
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • PCI-Express® 3.0 port with integrated PHY
    • One 2-lane gen2-compliant port
    • or two 1-lane gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC®/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRSM)
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-Pin BGA (ABC)
  • Architecture designed for ADAS applications
  • Video, image, and gaphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Orocessing Units (IPU)
  • Vision acceleration pac
    • Up to four Embedded Vision Engines (EVEs)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • 2-port gigabit ethernet (GMAC)
  • Enhanced Direct Memory Access (EDMA) controller
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • PCI-Express® 3.0 port with integrated PHY
    • One 2-lane gen2-compliant port
    • or two 1-lane gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC®/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRSM)
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-Pin BGA (ABC)

TI’s new TDA2x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm® Cortex®-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2x SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm® Cortex®-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2x SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.
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此產品系列適用於大量汽車製造商。如需詳細資訊，請與 TI 銷售代表聯繫。

進一步了解先進駕駛輔助系統 (ADAS) 的 TDAx SoC。

技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0 datasheet (Rev. F) PDF | HTML 2019年 6月 6日
* Errata TDA2x ADAS Applications Processor (Rev. K) PDF | HTML 2024年 9月 8日
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021年 5月 5日
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020年 8月 24日
White paper Paving the way to self-driving cars with ADAS (Rev. A) 2020年 7月 24日
White paper Stereo vision- facing the challenges and seeing the opportunities for ADAS (Rev. A) 2020年 7月 24日
User guide TDA2x ADAS Applications Processor Public Technical Reference Manual (Rev. G) 2020年 2月 22日
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020年 1月 6日
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019年 6月 11日
Application note TDA2x/TDA2E Performance (Rev. A) PDF | HTML 2019年 6月 10日
Application note The Implementation of YUV422 Output for SRV 2018年 8月 2日
Application note MMC DLL Tuning (Rev. B) 2018年 7月 31日
Application note Integrating AUTOSAR on TI SoC: Fundamentals 2018年 6月 18日
Application note ECC/EDC on TDAxx (Rev. B) 2018年 6月 13日
Application note Sharing VPE Between VISIONSDK and PSDKLA 2018年 5月 4日
Application note TMS320C66x XMC Memory Protection 2018年 1月 31日
Application note DSS Bit Exact Output (Rev. A) 2018年 1月 12日
Application note Flashing Utility - mflash 2018年 1月 9日
White paper Embedded low-power deep learning with TIDL 2017年 12月 8日
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017年 11月 7日
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017年 11月 3日
Application note DSS BT656 Workaround for TDA2x (Rev. A) 2017年 11月 3日
Functional safety information Safety Features on VisionSDK 2017年 10月 26日
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017年 9月 12日
White paper Step into next-gen architectures for multi-camera operations in automobiles 2017年 6月 16日
White paper Making Cars Safer Through Technology Innovation (Rev. A) 2017年 6月 7日
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016年 12月 15日
Application note Quad Channel Camera Application for Surround View and CMS Camera Systems (Rev. A) 2016年 8月 23日
Application note ADAS Power Management 2016年 3月 7日
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016年 2月 23日
User guide Vision Application Board User's Guide 2016年 2月 9日
White paper Surround view camera systems for ADAS (Rev. A) 2015年 10月 20日
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014年 8月 13日
White paper TI Vision SDK, Optimized Vision Libraries for ADAS Systems 2014年 4月 14日
White paper TI Gives Sight to Vision-Enabled Automotive Technologies 2013年 10月 16日
White paper Empowering Automotive Vision with TI’s Vision AccelerationPac 2013年 10月 13日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發套件

D3-3P-RVP-TDA2X — 適用於 TDA2 處理器的 D3 Embedded DesignCore® RVP-TDA2x 開發套件

RVP-TDA2x 是用於高階 ADAS 系統的多攝影機平台。它包括兩個 ARM A15 應用處理器、最多四個視覺加速 Pac (EVE) 協同處理器和一個硬體加速的 H.264 編碼器。開發套件支援八個攝影機輸入，但可以視需求自訂。套件購買包括軟體分發和一次性授權。

從：D3 Embedded
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軟體開發套件 (SDK)

PROCESSOR-SDK-RADAR — RTOS Processor SDK for Radar

Processor SDK-Vision (Vision SDK) and Processor SDK-Radar (Radar SDK) are multi-processor software development kits for TDAx processors. The software framework allows users to create different ADAS application data flows involving radar capture, radar processing, video capture, video (...)

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下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-VISION — Linux and RTOS Processor SDK for Vision

Processor SDK-Vision (Vision SDK) and Processor SDK-Radar (Radar SDK) are multi-processor software development kits for TDAx processors. The software framework allows users to create different ADAS application data flows involving radar capture, radar processing, video capture, video (...)

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應用軟體及架構

MOMENTA-3P-DL-ALGORITHMS — TDA4x 處理器上適用於 ADAS 前置攝影機應用的 Momenta 深度學習演算法

Momenta’s deep learning based algorithms for ADAS applications make full use of the DSP cores and accelerators on TDA4x for neural network processing. Designed to achieve market leading computational and power efficiency, Momenta’s algorithms offer an array of pre- and post-imaging (...)
從：Momenta
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程式碼範例或展示

D3-3P-DEV — 適用於 AI 相機、硬體、驅動程式與韌體的 D3 Embedded 支援

D3 Embedded 是一家總部位於美國的公司，專注於為高效能應用方式提供整合視覺和毫米波雷達感應、連結、嵌入式處理和人工智慧的端到端解決方案。D3 Embedded 擁有超過 25 年的開發經驗，提供客製化軟體和硬體的開發服務、ISP 架構影像調整、AI 和演算法以及複雜的 DSP 處理鏈開發服務。他們的專業雷達和 DSP 團隊專注於為德州儀器的應用特定處理器提供客製化軟體，其中包括功能強大的全新 C7x DSP。
從：D3 Embedded
View Options
IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
從：Green Hills Software
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作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS，專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構，能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
從：QNX Software Systems
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模擬型號

TDA2x BSDL Model

SPRM670.ZIP (28 KB) - BSDL Model
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模擬型號

TDA2x IBIS Model

SPRM671.ZIP (36408 KB) - IBIS Model
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模擬型號

TDA2x Thermal Model

SPRM672.ZIP (3 KB) - Thermal Model
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ABC) 760 Ultra Librarian
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  • MTBF/FIT 估算值
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