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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

AM2434

現行

四核心 Arm® Cortex®-R5F 架構 MCU，具有工業通訊功能和最高達 800 MHz 的安全性

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AM2434

現行
產品規格表 立即訂購

產品詳細資料

CPU Arm Cortex-R5F Frequency (MHz) 800 Certified protocol software stacks EnDat 2.2, EtherCAT, EtherNet/IP, IO-Link Features EtherCAT, EtherNet/IP, IO-Link, Integrated industrial protocols, Profinet, TSN Operating system FreeRTOS TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution LP8733, TPS65219 Operating temperature range (°C) -40 to 125 Ethernet Yes
CPU Arm Cortex-R5F Frequency (MHz) 800 Certified protocol software stacks EnDat 2.2, EtherCAT, EtherNet/IP, IO-Link Features EtherCAT, EtherNet/IP, IO-Link, Integrated industrial protocols, Profinet, TSN Operating system FreeRTOS TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution LP8733, TPS65219 Operating temperature range (°C) -40 to 125 Ethernet Yes
FCBGA (ALV) 441 295.84 mm² 17.2 x 17.2 FCCSP (ALX) 293 121 mm² 11 x 11
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800MHz, highly-integrated for real-time processing
    • Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
    • 32KB I-cache and 32KB D-cache per R5F core with SECDED ECC on all memories
    • Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
    • Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC
  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • On-Chip Debug functionality through JTAG and Trace interfaces)
  • Data Movement Subsystem (DMSS)
    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)
  • Time Sync Subsystem
    • Central Platform Time Sync (CPTS) module
    • Timer Manager (TIMERMANAGER) with 1024 timers
    • Time Sync and Compare event interrupt routers
  • 2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols
    • Backwards compatibility with 10/100Mb PRU-ICSS
    • Each PRU_ICSSG contains:
      • 3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)
        • PRU General Use core (PRU)
        • PRU Real-Time Unit core (PRU-RTU)
        • PRU Transmit core (PRU-TX)
      • Each PRU core supports the following features:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Up to 2× Ethernet ports
        • RGMII (10/100/1000)
        • MII (10/100)
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • 2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta Filter Module (SDFM) interfaces
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • 1× Enhanced Capture Module (ECAP)
      • 16550-compatible UART
        • Dedicated 192MHz clock to support 12Mbps PROFIBUS
  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× Universal Asynchronous Receive/Transmit (UART) modules
  • 1× 12-bit Analog-to-Digital Converters (ADC)
    • Configurable sample rate up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (SPI) controllers
  • 3× General-Purpose I/O (GPIO) modules
  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • 2× Fast Serial Interface Transmitter (FSITX) cores
  • 6× Fast Serial Interface Receiver (FSIRX) cores

High-speed interfaces:

  • 1× Integrated Ethernet switch supporting: (CPSW)
    • Up to 2 external Ethernet ports
      • RGMII (10/100/1000)
      • RMII (10/100)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB Host, USB Device, or USB Dual-Role device
    • USB Device: High-speed (480Mbps) and Full-speed (12Mbps)
    • USB Host: SuperSpeed Gen1 (5Gbps), High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)
    • Integrated USB VBUS detection
  • 1× Serializer/Deserializer (SERDES)
    • One SERDES PHY lane to support eitherPCI-Express Gen2 or USB SuperSpeed Gen1
  • 2× Multimedia Card/Secure Digital (MMCSD) interfaces
    • One 8-bit for eMMC (MMCSD0)
    • One 4-bit for MMCSD/SDIO (MMCSD1)
    • Integrated analog switch for voltage switching from 3.3V to 1.8V for high-speed cards
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-bit parallel bus with 133MHz clock or
    • 32-bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support
  • 1× Flash Subsystem (FSS) for external memory configurable as either:
    • 1× Octal SPI (OSPI) flash interface
    • or 1× Quad SPI (QSPI) flash interface
  • Simplified power sequencing requirements
  • Dual-voltage I/O Support (3.3V / 1.8V)
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for monitoring over-voltage and under-voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with dedicated error pin
    • ECC and parity on select internal bus interconnects
    • Run-time safety diagnostics, including:
      • Voltage, Temperature, and Clock Monitoring
      • Windowed Watchdog Timers
      • CRC Engine for memory integrity checks
    • MCU domain with dedicated memory, interfaces, and M4FSS capable of isolation from the larger SoC with Freedom From Interference (FFI) features:
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Controlled reset isolation
      • Dedicated MCU PLL and MMR control
      • Separate I/O voltage supply rail
  • Supports boot from OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, UART, I2C, MMCSD, eMMC, USB, PCIe, and Ethernet interfaces.
  • 16-nm FinFET technology
  • ALV: 17.2mm × 17.2mm, 0.8mm pitch(441-pin) [Lidded] Flip-Chip Ball Grid Array(FCBGA)
  • ALX: 11.0mm × 11.0mm, 0.5mm pitch(293-pin) [Overmolded] Flip-Chip Chip Scale Package(FCCSP) 
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800MHz, highly-integrated for real-time processing
    • Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
    • 32KB I-cache and 32KB D-cache per R5F core with SECDED ECC on all memories
    • Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
    • Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC
  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • On-Chip Debug functionality through JTAG and Trace interfaces)
  • Data Movement Subsystem (DMSS)
    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)
  • Time Sync Subsystem
    • Central Platform Time Sync (CPTS) module
    • Timer Manager (TIMERMANAGER) with 1024 timers
    • Time Sync and Compare event interrupt routers
  • 2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols
    • Backwards compatibility with 10/100Mb PRU-ICSS
    • Each PRU_ICSSG contains:
      • 3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)
        • PRU General Use core (PRU)
        • PRU Real-Time Unit core (PRU-RTU)
        • PRU Transmit core (PRU-TX)
      • Each PRU core supports the following features:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Up to 2× Ethernet ports
        • RGMII (10/100/1000)
        • MII (10/100)
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • 2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta Filter Module (SDFM) interfaces
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • 1× Enhanced Capture Module (ECAP)
      • 16550-compatible UART
        • Dedicated 192MHz clock to support 12Mbps PROFIBUS
  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× Universal Asynchronous Receive/Transmit (UART) modules
  • 1× 12-bit Analog-to-Digital Converters (ADC)
    • Configurable sample rate up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (SPI) controllers
  • 3× General-Purpose I/O (GPIO) modules
  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • 2× Fast Serial Interface Transmitter (FSITX) cores
  • 6× Fast Serial Interface Receiver (FSIRX) cores

High-speed interfaces:

  • 1× Integrated Ethernet switch supporting: (CPSW)
    • Up to 2 external Ethernet ports
      • RGMII (10/100/1000)
      • RMII (10/100)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB Host, USB Device, or USB Dual-Role device
    • USB Device: High-speed (480Mbps) and Full-speed (12Mbps)
    • USB Host: SuperSpeed Gen1 (5Gbps), High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)
    • Integrated USB VBUS detection
  • 1× Serializer/Deserializer (SERDES)
    • One SERDES PHY lane to support eitherPCI-Express Gen2 or USB SuperSpeed Gen1
  • 2× Multimedia Card/Secure Digital (MMCSD) interfaces
    • One 8-bit for eMMC (MMCSD0)
    • One 4-bit for MMCSD/SDIO (MMCSD1)
    • Integrated analog switch for voltage switching from 3.3V to 1.8V for high-speed cards
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-bit parallel bus with 133MHz clock or
    • 32-bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support
  • 1× Flash Subsystem (FSS) for external memory configurable as either:
    • 1× Octal SPI (OSPI) flash interface
    • or 1× Quad SPI (QSPI) flash interface
  • Simplified power sequencing requirements
  • Dual-voltage I/O Support (3.3V / 1.8V)
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for monitoring over-voltage and under-voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with dedicated error pin
    • ECC and parity on select internal bus interconnects
    • Run-time safety diagnostics, including:
      • Voltage, Temperature, and Clock Monitoring
      • Windowed Watchdog Timers
      • CRC Engine for memory integrity checks
    • MCU domain with dedicated memory, interfaces, and M4FSS capable of isolation from the larger SoC with Freedom From Interference (FFI) features:
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Controlled reset isolation
      • Dedicated MCU PLL and MMR control
      • Separate I/O voltage supply rail
  • Supports boot from OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, UART, I2C, MMCSD, eMMC, USB, PCIe, and Ethernet interfaces.
  • 16-nm FinFET technology
  • ALV: 17.2mm × 17.2mm, 0.8mm pitch(441-pin) [Lidded] Flip-Chip Ball Grid Array(FCBGA)
  • ALX: 11.0mm × 11.0mm, 0.5mm pitch(293-pin) [Overmolded] Flip-Chip Chip Scale Package(FCCSP) 

AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.

The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory (TCM) banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.

The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.

AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.

The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory (TCM) banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.

The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.
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重要文件 類型 標題 格式選項 日期
* Data sheet AM243x Sitara™ Microcontrollers datasheet (Rev. H) PDF | HTML 2025年 12月 19日
* Errata AM64x/AM243x Processor Silicon Revision 1.0, 2.0 (Rev. J) PDF | HTML 2025年 11月 13日
Application brief Next-Gen Industrial Monitoring: AI-Driven Communication and Fault Prevention PDF | HTML 2026年 2月 26日
Application note HSR/PRP Solutions on Sitara Processors for Grid Substation Communication (Rev. A) PDF | HTML 2026年 1月 30日
Application note Getting Started with Sysconfig Tool PDF | HTML 2025年 11月 21日
User guide Hardware Design Considerations for Custom Board Using AM6442, AM6422, AM6412 and AM2434 (ALV, ALX) Processor (Rev. D) PDF | HTML 2025年 10月 24日
User guide AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist (Rev. E) PDF | HTML 2025年 10月 10日
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2025年 9月 5日
Application note Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 2025年 9月 3日
Functional safety information AM6x, AM24x Software Diagnostics Library TÜV SÜD Functional Safety Certificate for 9.2.0 SDK (Rev. A) 2025年 7月 17日
Application note Processors Tools Overview PDF | HTML 2025年 6月 16日
White paper Real-Time Communication for Industrial Applications PDF | HTML 2024年 10月 1日
White paper Functional Safety Support for Arm®-based Microcontrollers and Processors (Rev. A) PDF | HTML 2024年 5月 10日
Functional safety information AM64x, AM243x IEC61508 TUV SUD Functional Safety Certificate 2024年 3月 25日
Application note Serial and Parallel Port Implementation With Programmable Real-Time Unit (PRU) PDF | HTML 2024年 3月 20日
Product overview AM243x OSPI, QSPI Flash Selection Guide (Rev. A) PDF | HTML 2024年 2月 6日
Application note Sitara™AM64x /AM243x BenchmarksCortex-R5 Memory Access Latency (Rev. B) PDF | HTML 2024年 1月 24日
Product overview Industrial Communication Protocol Support for Arm®-based Microcontrollers and Processors PDF | HTML 2023年 12月 22日
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 2023年 11月 15日
Product overview Functional Safety for AM2x and Hercules™ Microcontrollers PDF | HTML 2023年 11月 8日
User guide AM64x/AM243x Technical Reference Manual (Rev. H) 2023年 11月 1日
Application note Sitara MCU Thermal Design PDF | HTML 2023年 9月 11日
Application brief EtherCAT Connected Motor Drive System With Endat 2.2 Absolute Encoder Feedback PDF | HTML 2023年 9月 7日
Application note Integration of MbedTLS on SITARA MCU Devices PDF | HTML 2023年 8月 3日
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 2023年 7月 31日
User guide 10-kW, Three-Phase, Three-Level (T-Type) Inverter Using AM263 PDF | HTML 2023年 7月 11日
Certificate BP-AM2BLDCSERVO EU Declaration of Conformity (DoC) 2023年 6月 28日
Application note Powering the AM243x With the TPS65219 PMIC PDF | HTML 2023年 6月 26日
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023年 5月 24日
Application note Four Channel Analog to Digital Interface with Sitara AM243x MCU+ PDF | HTML 2023年 4月 20日
Application note Single Pair Ethernet with Power Over Data Line PDF | HTML 2023年 4月 20日
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
Application note FSI Bandwidth-Optimization for Multi-axis Servo Control PDF | HTML 2022年 12月 14日
Application note Debugging Sitara AM2x Microcontrollers PDF | HTML 2022年 10月 24日
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022年 10月 11日
Application note Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 2022年 8月 8日
Application note AM64x/AM243x Extended Power-On Hours PDF | HTML 2022年 8月 5日
Technical article What is “real-time control” and why do you need it? PDF | HTML 2022年 4月 6日
Application note AM243x/AM64x Single Chip Motor Control Benchmark PDF | HTML 2022年 3月 30日
Technical article Factory automation design made simple with multiprotocol industrial Ethernet syste PDF | HTML 2022年 3月 15日
Application note Using LP8733xx and TPS65218xx PMICs to Power AM64x and AM243x Sitara Processors PDF | HTML 2022年 2月 16日
White paper 運用適合工業 4.0 Sitara™ 伺服驅動器的處理器與微控制器 (Rev. C) PDF | HTML 2022年 1月 12日
Technical article 5 ways high-performance MCUs are reshaping the industry PDF | HTML 2021年 7月 12日
Application note AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) PDF | HTML 2021年 7月 1日
Application note AM64x/AM243x Power Estimation Tool (Rev. A) PDF | HTML 2021年 7月 1日
More literature LaunchPad™ kit with Sitara™ AM243x MCU Pinout Map 2021年 6月 18日
White paper 以 Sitara™ AM2x MCU 顛覆即時控制、網路與分析效能 2021年 6月 13日
User guide AM64x/AM243x BGA Escape Routing (Rev. A) PDF | HTML 2021年 4月 6日
Functional safety information The state of functional safety in Industry 4.0 2018年 11月 27日

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開發板

BOOSTXL-IOLINKM-8 — 八埠 IO-Link 主要裝置 BoosterPack™

此 BoosterPack™ 專為搭配 LP-AM243 TI LaunchPad™ 套件及 Sitara™ AM243x MCU 運作。此設計採用具快速且決定性時脈、獨立週期與位元率配置的八埠 IO-Link 主要裝置。此設計可用於建立遠端 IO 閘道，以連接 OPC UA、Profinet、EtherCAT 或乙太網路 IP。適用 Sitara™ 處理器基礎訊框處理程式的可編程即時單元 (PRU) 可提供靈活的時脈與同步控制方式。

使用指南: PDF
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開發板

BP-AM2BLDCSERVO — AM2x Brushless-DC (BLDC) Servo Motor BoosterPack

The AM2x BLDC Servo Motor BoosterPack plug-in module is an add-on for the AM2x LaunchPad development kits. This BoosterPack provides up to two axes of 24V/8A BLDC driver, ADC/SDFM current feedback, industrial absolute encoder, and resolver feedback. 

使用指南: PDF | HTML
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開發板

LP-AM243 — 適用 Arm® 架構 MCU 的 AM243x 通用 LaunchPad™ 開發套件

LP-AM243 為適用於 AM243x 系列之 Sitara™ 高效能微控制器的開發電路板。此電路板極適用於初始評估與原型，因為它提供標準化且使用方便的平台，可用於開發您的下一個應用程式。LP-AM243 配備體積較小的 Sitara AM2434 ALX 微控制器單元 (MCU) 及其它零組件，可讓使用者使用各種裝置介面，包括工業乙太網路、標準乙太網路、快速序列介面 (FSI) 及其它介面，以輕鬆建立原型。

AM2434 支援 EtherCAT、EtherNet/IP 和 PROFINET 等各種工業乙太網路通訊協定。此 LaunchPad™ 提供比 TMDS243EVM (...)

使用指南: PDF | HTML
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開發板

RIO-DEV-PLATFORM — Remote IO development platform for Arm-based MCUs with industrial Ethernet

The Remote IO Development Platform provides tailored combinations of hardware and software designed to make it quick and easy to establish remote I/O connections for a variety of applications. This platform can be used to build a remote IO gateway to connect to industrial protocols such as (...)

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開發板

TMDS243DC01EVM — 適用於高速擴展的 AM243x 與 AM64x 評估模組斷路板

TMDS243DC01EVM 是適用於 AM243x 產品的高速擴充 (HSE) 評估模組 (EVM)。此 EVM 是 AM243x EVM（TMDS243EVM）的附加板。

TMDS243DC01EVM 包含通用訊號中斷，提供對來自 TMDS243EVM 的 HSE 接頭包含的所有 I/O 訊號的測試存取。此擴充板配備 150 針腳 HSE 接頭和 20 針腳類比轉數位轉換器 (ADC) 接頭，可搭配 TMDS243EVM 使用。

使用指南: PDF | HTML
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開發板

TMDS243EVM — 適用於 Arm® Cortex®-R5F 架構 MCU 的 AM243x 評估模組

TMDS243 評估模組 (EVM) 是一套獨立的測試及開發平台，可評估 AM243x 功能，並為各種應用開發原型。TMDS243EVM 配備了外型更大的 Sitara™ AM2434 ALV 微控制器單元 (MCU) 及其他零組件，可讓使用者運用 MCU 的安全功能及各種裝置介面，其中包括工業乙太網路、標準乙太網路、快捷外設互聯標準 (PCIe)、快速序列介面 (FSI) 及其他功能，協助輕鬆建立原型。此 EVM 提供比 LP-AM243 LaunchPad™ 更大的周邊設備組，原因是配備了體積較大的 AM243 ALV 封裝。

車載顯示器使用 AM243x 序列周邊介面 (SPI) (...)

使用指南: PDF | HTML
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開發板

TMDS64DC01EVM — AM64x IO-Link 和高速分接板

The AM64x IO-Link and high speed expansion board is an add-on module for the AM64x GP EVM.  This board includes eight (8) IO-Link ports and general purpose signal breakout.  The Breakout board section provides the test access to all the IO signals included on the High Speed Expansion (...)

使用指南: PDF | HTML
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開發板

PHYTC-3P-KIT-AM64 — phyBOARD®-AM64x 開發套件

phyBOARD®-AM64x 開發套件是一款系統模組 (SOM) 和載板，採用 phyCORE®-AM64x，這是一款強大且可靠的嵌入式處理器板，適用於無顯示工業通訊系統。50 mm x 37 mm SOM 具有廣泛的 280 接腳互連，可支援常見工廠通訊協定 (如 CAN、EtherCAT、UART、I2C)，也支援自動化特定介面 (如 EPWM、ECAP 及 EQEP)。由於 TI AM64x 處理器的異質架構，您可使用 Linux 執行大部分應用程式，並將關鍵元件卸載至專業低延遲同級最佳即時核心。

從：PHYTEC
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開發板

TQ-3P-SITARASOMS — 適用於 TI Arm 架構處理器和微控制器的 TQ Group 系統模組

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
從：TQ-Group
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開發板

TQ-3P-SOM-TQMA243XL — TQ-Group TQMa243xL system on module for AM2434 Arm-based microcontroller

The embedded module TQMA243XL, is based on the processor family AM243x quad-core Arm® Cortex®-R5F-based MCU. This LGA (land grid array) module is designed to use the pin compatible processors on one module design. This module is ideally suited for headless applications with extended (...)

從：TQ-Group
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偵錯探測器

TMDSEMU110-U — XDS110 JTAG 偵錯探測器

德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別，適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列，可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。同時，所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。  對於針腳上的核心追蹤，則需要 XDS560v2 PRO TRACE。

德州儀器 XDS110 透過 TI 20 針腳連接器（具有用於 TI 14 針腳和 Arm 10 針腳和 Arm 20 針腳的多轉接器）連接到目標電路板，並透過 USB2.0 (...)

使用指南: PDF
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偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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偵錯探測器

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

從：TASKING Germany GmbH
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軟體開發套件 (SDK)

IBV-3P-ICECAT — 適用於嵌入式系統的 IBV EtherCAT MainDevice SDK

The icECAT EtherCAT Master Stack library by IBV is a Software Development Kit (SDK) for creating an EtherCAT MainDevice (master) system achieving best performance with lowest resource usage. It is especially designed for use on embedded systems with optimized Link Layer drivers with DMA support (...)
從：IBV - Echtzeit- und Embedded GmbH & Co. KG
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軟體開發套件 (SDK)

INDUSTRIAL-COMMUNICATIONS-SDK-AM243X — Industrial Communications SDK for AM243x - RTOS

This software development kit (SDK) includes real-time industrial communication protocols (EtherCAT, EtherNet/IP, PROFINET, IO-Link, etc.) on TI processors. It also has PRU-ICSS firmware, drivers, communication stack libraries, and application examples, along with documentation.

What's new:

  • (...)
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軟體開發套件 (SDK)

MCU-PLUS-SDK-AM243X — MCU+ SDK for AM243x – RTOS, No-RTOS

The AM243x microcontroller (MCU) software is a collection of software development kits (SDK) providing a software platform for TI embedded processors with easy setup and fast out-of-the-box access to examples, benchmarks and demonstrations. This software accelerates application development (...)

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軟體開發套件 (SDK)

MOTOR-CONTROL-SDK-AM243X — Motor Control SDK for AM243x - RTOS

The AM243x microcontroller (MCU) software is a collection of software development kits (SDK) providing a software platform for TI embedded processors with easy setup and fast out-of-the-box access to examples, benchmarks and demonstrations. This software accelerates application development (...)

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韌體

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM 韌體

SecIC-HSM 旨在滿足 MCU/SoC 晶片所需的網路安全要求。HSM 韌體可應用於汽車、新能源、光伏、機器人、醫療保健與航空等領域。提供的網路安全功能包括安全開機、安全通訊 (SecOC)、安全診斷、安全儲存、安全更新、安全偵錯和金鑰管理。SecIC-HSM 的優點：一站式網路安全解決方案，具備跨晶片系列的全方位軟體相容性，擁有業界領先的性能，已在近 30 家 OEM 的量產車型中成功部署，累計出貨超過 300 萬套。
從：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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快速入門

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development tool ecosystem. It is an integrated development environment (IDE) for TI's microcontrollers, processors, wireless connectivity devices and radar sensors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize (...)

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IDE、配置、編譯器或偵錯程式

DDR-CONFIG-AM24 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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IDE、配置、編譯器或偵錯程式

IAR-KICKSTART — IAR Embedded Workbench

IAR Embedded Workbench delivers a complete development toolchain for building and debugging embedded applications for your selected target microcontroller. The included IAR C/C++ Compiler generates highly optimized code for your application, and the C-SPY Debugger is a fully integrated debugger for (...)
從：IAR Systems
使用指南: PDF
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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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線上培訓

AM24X-ACADEMY — AM24x Academy

AM24x Academy features easy-to-use training modules ranging from the basics of getting started to advanced development topics.
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作業系統 (OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
從：Green Hills Software
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軟體程式設計工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces.

UniFlash can be run from the cloud on the TI Developer Zone or downloaded and used (...)

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支援軟體

SPRCAJ9 — AM243x SW Build Sheet

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模擬型號

AM243x BSDL Model

SPRM781.ZIP (17 KB) - BSDL Model
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模擬型號

AM243x IBIS model (Rev. B)

SPRM783B.ZIP (263 KB) - IBIS Model
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模擬型號

AM243x Thermal Model

SPRM782.ZIP (1 KB) - Thermal Model
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模擬型號

AM64x/AM243x BSDL Model

SPRM732.ZIP (21 KB) - BSDL Model
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模擬型號

AM64x/AM243x IBIS Model (Rev. E)

SPRM730E.ZIP (1889 KB) - IBIS Model
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模擬型號

AM64x/AM243x SR2.0 BSDL Model

SPRM811.ZIP (21 KB) - BSDL Model
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計算工具

SPRM779 — AM64x Power Estimation Tool

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參考設計

TIDA-010261 — 具有數據線供電能力的 10BASE-T1L 單對乙太網路感測器參考設計

此參考設計說明包含數據線供電能力 (PoDL) 的單對乙太網路 (SPE) 通訊後端實作。此設計使用 Sitara™ AM2434 MCU，在一側介接類比前端，並於另一側介接乙太網路實體 (PHY) 層。強大的 MCU 不僅可以將感測器資料轉送至乙太網路，還可以在邊緣進行資料處理。
Design guide: PDF
參考設計

TIDA-010948 — 具有位置回饋和工業通訊協定的 6 軸馬達控制參考設計

此參考設計展現了使用兩部 TI Sitara™ MCU-AM243x 裝置處理 6 軸控制馬達驅動器的能力。該馬達驅動器透過簡單開放即時乙太網路 Gigabit (SORTE_G) 連線。此設計包括 AM243x 裝置上的 800MHz R5F 核心，可針對具有增量式編碼器的 6 個獨立馬達，以 62.5μs 週期時間執行閉合迴路磁場定向控制。此 AM243x 的一個可編程即時單元 (PRU) 核心可充當 SORTE_G 控制器，傳送要求並接收 6 軸馬達的角度資料。另一個 AM243x 裝置的 PRU 核心則可充當 SORTE_G 裝置，負責傳送 6 軸馬達角度資料。這些資料將由此 (...)
Design guide: PDF
參考設計

TIDEP-01032 — EtherCAT® 連線、單晶片、雙伺服馬達驅動參考設計

此參考設計展示 AM243x 如何支援完全整合的即時伺服馬達驅動控制及工業通訊路徑。此路徑會從接收 EtherCAT® CiA402 目標速度命令，到對雙連接馬達執行閉合迴路 FOC 速度控制，再到將實際速度值傳回到 EtherCAT PLC。
Design guide: PDF
參考設計

TIDA-010234 — 八埠 IO-Link 主要參考設計

此參考設計採用具快速且決定性時脈的 IO-Link 主要裝置，並搭載 8 個連接埠。每個連接埠均可以獨立位元率和週期時脈運作。此設計可用於建立遠端 IO 閘道，以連接 OPC UA、Profinet、EtherCAT 或乙太網路 IP。以 PRU 為基礎的訊框處理程式可提供時序靈活性與同步。
Design guide: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ALV) 441 Ultra Librarian
FCCSP (ALX) 293 Ultra Librarian
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