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AM2754-Q1

現行

具有四核心 ARM® Cortex®-R5F、10.75MB SRAM 且適用於汽車音訊的 80GFLOPS DSP 微控制器

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AM2754-Q1

現行
產品規格表 立即訂購

產品詳細資料

CPU Arm-Cortex - R5F Features Hardware ASRC, Multichannel audio serial ports (McASP) Operating system RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage Rating Automotive Operating temperature range (°C) to
CPU Arm-Cortex - R5F Features Hardware ASRC, Multichannel audio serial ports (McASP) Operating system RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage Rating Automotive Operating temperature range (°C) to
FCCSP (ANJ) 361 249.64 mm² 15.8 x 15.8
  • Dual or Quad-core Arm Cortex R5F CPU with each core running up to 1GHz
    • 32KB I-Cache with 64-bit ECC per CPU core
      • 4x8KB association
      • Single Error Correction, Double Error Detection ECC protected per 64 bits
    • 32KB D-cache with 64-bit ECC per CPU core
      • 4x8KB association
      • Single Error Correction, Double Error Detection ECC protected per 64 bits
    • 64KB Tightly Coupled Memory (TCM) per core, with 32-bit ECC
      • Single Error Correction, Double Error Detection ECC protected per 64 bits
      • Two Banks, A and B, 32KB each
        • Bank B split into B0 and B1, 16KB each
      • 128KB TCM for CPU0 in lockstep mode
    • Up to 128KB Remote L2 Cache
      • 32B cache line
      • Up to 128KB L2 cache covering up to 16MB cacheable space
      • Read only, 8-way cache
      • Fast Local Copy (FLC) support
    • For each cluster, lockstep or independent dual core operation supported
  • Single or Dual C7x DSP core with each core running up to 1GHz
    • L1 memory architecture
      • 32KB I-Cache per core
      • 64KB D-Cache per core
    • L2 memory architecture
      • 2.25MB with ECC protection on L2 SRAM
        • 2MB "Main" segment
        • 256KB "Auxiliary" segment
    • Matrix Multiply Accelerator Version 2f (MMA2F) on DSP0
  • 2x Asynchronous Audio Sample Rate Converter (ASRC)
    • 140dB Signal-to-Noise ratio (SNR)
    • Up to 8 pairs of input and output streams (up to 16 channels total) per ASRC
    • Input and output sample rates from 8KHz to 216KHz
    • 16-, 18-, 20-, 24-bit data input/output

Memory Subsystem:

  • Up to 6MB of On-Chip Shared SRAM

  • Remote Low latency L2 cache (RL2), software programmable, allocated from SRAM

  • 432KB of On-Chip SRAM in SMS Subsystem
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
  • 2 × Flash Sub Systems (FSS) that support Octal Serial Peripheral Interface (OSPI) at up to 166MHz SDR and 166MHz DDR at 1.8V and 3.3V with full XIP (eXecute In Place) which can be used for
    • 1x FSS supporting OSPI OptiFlash memory technology, Firmware Over-The-Air upgrades (FOTA), and On The Fly Advanced Encryption Standard (OTFA)
    • 1x FSS supporting OSPI or HyperRAM
    • RAM expansion
  • 1 × 8-bit Multi-Media Card/Secure Digital (eMMC/SD) interface
  • 5 × Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 26 Serial Data Pins across 5x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S) and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 8 × Universal Asynchronous RX-TX (UART) modules
  • 5 × Serial Peripheral Interface (SPI) controllers
  • 8 × Inter-Integrated Circuit (I2C) ports
  • 5 × Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 3 × Enhanced Pulse Width Modulation (ePWM) modules
  • 6 × Enhanced Capture (ECAP) modules
  • 1 × 12-bit Analog to Digital Converters (ADC) with 4MSPS maximum sampling rate
  • Up to 167 General Purpose I/O (GPIO)
  • Integrated Ethernet Switch supporting (total 2 external ports)
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE 1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Supports 802.1Qav (eAVB)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority flow control
    • Four CPU hardware interrupt pacing
    • IP/ UDP/ TCP checksum offload in hardware
  • USB 2.0
    • Port configurable as USB host, USB device, or USB Dual-Role device
    • Integrated USB VBUS detection
  • Hardware Security Module (HSM)
    • Dedicated dual-core ARM Cortex-M4F Security co-processor with dedicated interconnect for security
    • Dedicated security DMA and IPC subsystem for isolated processing
  • Secure boot support
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES - 128/192/256-bit key sizes
      • SHA2 - 224/256/384/512-bit support
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing: RSA-4096 bits, ECDSA, SM2DSA, Curve25519/448
      • Supports Chinese crypto algorithms: SM3 and SM4
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-Fly encryption and support for OSPI interface in XIP mode
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D targeted
    • Hardware integrity up to ASIL-B targeted
    • Safety-related certification
      • ISO 26262 planned
  • Power modes supported by Device Manager:
    • Active
    • Standby
    • IO Retention
  • UART
  • I2C EEPROM
  • OSPI NOR/NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass Storage
  • USB (device) boot from external host (DFU mode)
  • Ethernet
  • AEC-Q100 qualified for automotive applications
  • 16-nm FinFET technology
  • 15.8mm x 15.8mm, 0.8mm pitch 361-pin FCCSP
  • Dual or Quad-core Arm Cortex R5F CPU with each core running up to 1GHz
    • 32KB I-Cache with 64-bit ECC per CPU core
      • 4x8KB association
      • Single Error Correction, Double Error Detection ECC protected per 64 bits
    • 32KB D-cache with 64-bit ECC per CPU core
      • 4x8KB association
      • Single Error Correction, Double Error Detection ECC protected per 64 bits
    • 64KB Tightly Coupled Memory (TCM) per core, with 32-bit ECC
      • Single Error Correction, Double Error Detection ECC protected per 64 bits
      • Two Banks, A and B, 32KB each
        • Bank B split into B0 and B1, 16KB each
      • 128KB TCM for CPU0 in lockstep mode
    • Up to 128KB Remote L2 Cache
      • 32B cache line
      • Up to 128KB L2 cache covering up to 16MB cacheable space
      • Read only, 8-way cache
      • Fast Local Copy (FLC) support
    • For each cluster, lockstep or independent dual core operation supported
  • Single or Dual C7x DSP core with each core running up to 1GHz
    • L1 memory architecture
      • 32KB I-Cache per core
      • 64KB D-Cache per core
    • L2 memory architecture
      • 2.25MB with ECC protection on L2 SRAM
        • 2MB "Main" segment
        • 256KB "Auxiliary" segment
    • Matrix Multiply Accelerator Version 2f (MMA2F) on DSP0
  • 2x Asynchronous Audio Sample Rate Converter (ASRC)
    • 140dB Signal-to-Noise ratio (SNR)
    • Up to 8 pairs of input and output streams (up to 16 channels total) per ASRC
    • Input and output sample rates from 8KHz to 216KHz
    • 16-, 18-, 20-, 24-bit data input/output

Memory Subsystem:

  • Up to 6MB of On-Chip Shared SRAM

  • Remote Low latency L2 cache (RL2), software programmable, allocated from SRAM

  • 432KB of On-Chip SRAM in SMS Subsystem
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
  • 2 × Flash Sub Systems (FSS) that support Octal Serial Peripheral Interface (OSPI) at up to 166MHz SDR and 166MHz DDR at 1.8V and 3.3V with full XIP (eXecute In Place) which can be used for
    • 1x FSS supporting OSPI OptiFlash memory technology, Firmware Over-The-Air upgrades (FOTA), and On The Fly Advanced Encryption Standard (OTFA)
    • 1x FSS supporting OSPI or HyperRAM
    • RAM expansion
  • 1 × 8-bit Multi-Media Card/Secure Digital (eMMC/SD) interface
  • 5 × Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 26 Serial Data Pins across 5x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S) and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 8 × Universal Asynchronous RX-TX (UART) modules
  • 5 × Serial Peripheral Interface (SPI) controllers
  • 8 × Inter-Integrated Circuit (I2C) ports
  • 5 × Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 3 × Enhanced Pulse Width Modulation (ePWM) modules
  • 6 × Enhanced Capture (ECAP) modules
  • 1 × 12-bit Analog to Digital Converters (ADC) with 4MSPS maximum sampling rate
  • Up to 167 General Purpose I/O (GPIO)
  • Integrated Ethernet Switch supporting (total 2 external ports)
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE 1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Supports 802.1Qav (eAVB)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority flow control
    • Four CPU hardware interrupt pacing
    • IP/ UDP/ TCP checksum offload in hardware
  • USB 2.0
    • Port configurable as USB host, USB device, or USB Dual-Role device
    • Integrated USB VBUS detection
  • Hardware Security Module (HSM)
    • Dedicated dual-core ARM Cortex-M4F Security co-processor with dedicated interconnect for security
    • Dedicated security DMA and IPC subsystem for isolated processing
  • Secure boot support
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES - 128/192/256-bit key sizes
      • SHA2 - 224/256/384/512-bit support
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing: RSA-4096 bits, ECDSA, SM2DSA, Curve25519/448
      • Supports Chinese crypto algorithms: SM3 and SM4
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-Fly encryption and support for OSPI interface in XIP mode
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D targeted
    • Hardware integrity up to ASIL-B targeted
    • Safety-related certification
      • ISO 26262 planned
  • Power modes supported by Device Manager:
    • Active
    • Standby
    • IO Retention
  • UART
  • I2C EEPROM
  • OSPI NOR/NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass Storage
  • USB (device) boot from external host (DFU mode)
  • Ethernet
  • AEC-Q100 qualified for automotive applications
  • 16-nm FinFET technology
  • 15.8mm x 15.8mm, 0.8mm pitch 361-pin FCCSP

The AM275x family of highly-integrated, high-performance microcontrollers is based on the Arm Cortex R5F and C7x floating point DSP cores. The microcontrollers enable original equipment manufacturers (OEM) and original design manufacturers (ODM) to quickly bring to market devices with robust software support and rich user interfaces. The device offers the maximum flexibility of a fully integrated, mixed processor design

Key features and benefits:

  • Extensive audio interfacing with 5x McASP peripherals
  • Peripherals supporting system level connectivity such as 2-port Gigabit Ethernet, USB, OSPI/QSPI, CAN-FD, UARTs, SPI and GPIOs.
  • Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM).
  • One or two dual-core R5F clusters with 128KB TCM per cluster (64KB per core) and up to two C7x DSP cores with 2.25MB of L2 SRAM per C7x DSP, greatly reducing the need for external memory.

The AM275x family of highly-integrated, high-performance microcontrollers is based on the Arm Cortex R5F and C7x floating point DSP cores. The microcontrollers enable original equipment manufacturers (OEM) and original design manufacturers (ODM) to quickly bring to market devices with robust software support and rich user interfaces. The device offers the maximum flexibility of a fully integrated, mixed processor design

Key features and benefits:

  • Extensive audio interfacing with 5x McASP peripherals
  • Peripherals supporting system level connectivity such as 2-port Gigabit Ethernet, USB, OSPI/QSPI, CAN-FD, UARTs, SPI and GPIOs.
  • Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM).
  • One or two dual-core R5F clusters with 128KB TCM per cluster (64KB per core) and up to two C7x DSP cores with 2.25MB of L2 SRAM per C7x DSP, greatly reducing the need for external memory.
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技術文件

star =TI 所選的此產品重要文件
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重要文件 類型 標題 格式選項 日期
* Data sheet AM275x Signal Processing Microcontrollers datasheet (Rev. A) PDF | HTML 2025年 7月 27日
* Errata AM275x Errata (Rev. A) PDF | HTML 2025年 7月 29日
* User guide AM275x Technical Reference Manual (Rev. A) PDF | HTML 2025年 8月 19日
Application note Throughput Characterization of OSPI and QSPI Serial NOR/NAND Flash Operations PDF | HTML 2026年 2月 17日
Application note AM275x Audio Design Guide PDF | HTML 2025年 11月 20日
Application brief AM275x Power Estimation Tool PDF | HTML 2025年 10月 20日
Technical article TI AM275x Audio DSP: Reshape In-Vehicle Audio Technology PDF | HTML 2025年 9月 25日
White paper 用於高端汽車音訊的高度整合 DSP 如何重新定義駕駛體驗 PDF | HTML 2025年 4月 17日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

AUDIO-AM275-EVM — AM275x 音訊評估模組

AM275x 評估模組 (EVM) 是獨立的測試、開發與評估平台，可供開發人員評估 AM275x 功能，並為各種多通道音訊應用開發原型。AM275x EVM 配備 AM275x 微控制器及其他元件，可讓使用者使用各種裝置介面，包括 McASP 數位音訊訊號、乙太網路、USB 2.0、CAN-FD 及其他介面，以輕鬆建立原型，並且具備板載電流測量功能，可監控功耗。提供的 USB 纜線搭配嵌入式模擬邏輯，可使用如 Code Composer Studio™ (CCSTUDIO) 等標準開發工具來進行模擬與偵錯。此 EVM 包含擴充連接器，可介接各種 TI 乙太網路擴充卡，展示 AM275x (...)
使用指南: PDF | HTML
TI.com 無法提供
開發板

DP83867-EVM-AM — 適用於工業乙太網路 PHY 附加電路板的 AM2x 及 AM6x 評估模組

DP83867-EVM-AM 是一款工業乙太網路 PHY 附加電路板，可搭配 Arm-b高性能微控制器評估模組使用。此附加電路板是使用 EVM 進行初始乙太網路評估與原型設計的絕佳選擇。DP83867-EVM-AM 配備了有 RGMII 介面的 TI DP83867IR 低延遲 10/100/1000-Mbps PHY，以及標準 RJ45 乙太網路連網連接器。具有乙太網路擴充連接器的 EVM (如 AUDIO-AM275-EVM) 支援 DP83867-EVM-AM。

使用指南: PDF | HTML
TI.com 無法提供
開發板

TAS67CD-AEC — TAS67CD-AEC D 類放大器音訊擴充卡

TAS67CD-AEC 為一款附加型介面卡，內建兩顆 4 通道 TAS67x D 類音訊放大器 IC，可透過音訊擴充卡 (AEC) 外型規格接頭，與 TI 的音訊 DSP EVM 相容接用。每張介面卡最多可提供 8 通道、
使用指南: PDF | HTML
TI.com 無法提供
偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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軟體開發套件 (SDK)

AM275-AWE-SDK — Audio Weaver SDK based on AM275

This SDK provides a cohesive platform for audio signal chain processing by integrating with DSP Concepts' Audio Weaver (AWE). It includes the AM275-FREERTOS-SDK, low level drivers, and examples for audio signal chain layouts.
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軟體開發套件 (SDK)

AM275-FREERTOS-SDK — FreeRTOS SDK for AM275 – RTOS, No-RTOS

This SDK contains the fundamental libraries, tools, and examples to develop RTOS and no-RTOS based applications, accompanied by "getting started" and developer user guides for AM275 peripherals
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驅動程式或資料庫

AM275X-RESTRICTED-DOCS-ADVANCE — AM275 Hardware Design Guidelines and Schematic Checklist

This NDA required folder will be updated regularly to contain all collaterals not yet approved for TI.com availability. This folder includes Hardware Design Guidelines and Schematic Checklist.
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快速入門

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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C7000-CGT — C7000 code generation tools (CGT) - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)

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C7000-SAFETI-CQKIT-RV — C7000 safety compiler qualification kit (leverages compiler release validations)

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
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SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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線上培訓

AM27X-ACADEMY — AM27x Academy

AM27x Academy features easy-to-use training modules ranging from the basics of getting started to advanced development topics.
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模擬型號

AM275x BSDL Model

SPRM883.ZIP (7 KB) - BSDL Model
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模擬型號

AM275x IBIS Model

SPRM885.ZIP (153 KB) - IBIS Model
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模擬型號

AM275x Thermal Model

SPRM884.ZIP (1 KB) - Thermal Model
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FCCSP (ANJ) 361 Ultra Librarian
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