AM625SIP
Processor Cores:
- Up to Quad 64-bit Arm
Cortex-A53 microprocessor subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache withParity protection
- Single-core Arm® Cortex®-M4F MCU at up to400MHz
- 256KB SRAM with SECDED ECC
- Dedicated Device/Power Manager
Multimedia:
- Display subsystem
- Dual display support
- 1920x1080 @ 60fps for each display
- 1x 2048x1080 + 1x 1280x720
- Up to 165MHz pixel clock support with Independent PLL for each display
- OLDI (4 lanes LVDS - 2x) andDPI (24-bit RGB LVCMOS)
- Support safety feature such as freeze frame detection and MISR data check
- 3D Graphics Processing Unit
- 1 pixel per clock or higher
- Fillrate greater than 500Mpixels/sec
- >500 MTexels/s, >8GFLOPs
- Supports at least 2 composition layers
- Supports up to 2048x1080 @60fps
- Supports ARGB32, RGB565 and YUV formats
- 2D graphics capable
- OpenGL ES 3.1, Vulkan 1.2
- One Camera Serial interface
(CSI-Rx) - 4 Lane with DPHY
- MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
- Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane
- ECC verification/correction with CRC check + ECC on RAM
- Virtual Channel support (up to 16)
- Ability to write stream data directly to DDR via DMA
Memory Subsystem:
- Up to 816KB of On-chip RAM
- 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
- 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
- 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
- 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
- 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
- DDR Subsystem (DDRSS)
- Integrated 512MB LPDDR4 SDRAM
- Supports speeds up to 1600MT/s
- 16-Bit data bus with inline ECC
Security:
- Secure boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
- Trusted Execution Environment
(TEE) supported
- Arm TrustZone based TEE
- Extensive firewall support for isolation
- Secure watchdog/timer/IPC
- Secure storage support
- Replay Protected Memory Block (RPMB) support
- Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
- Cryptographic acceleration
supported
- Session-aware
cryptographic engine with ability to auto-switch key-material based on
incoming data stream
- Supports cryptographic cores
- AES – 128-/192-/256-Bit key sizes
- SHA2 – 224-/256-/384-/512-Bit key sizes
- DRBG with true random number generator
- PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
- Session-aware
cryptographic engine with ability to auto-switch key-material based on
incoming data stream
- Debugging security
- Secure software controlled debug access
- Security aware debugging
PRU Subsystem:
- Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHz
- Intended for driving GPIO for
cycle accurate protocols such as additional:
- General Purpose Input/Output (GPIO)
- UARTs
- I2C
- External ADC
- 16KByte program memory per PRU withSECDED ECC
- 8KB data memory per PRU with SECDED ECC
- 32KB general purpose memory withSECDED ECC
- CRC32/16 HW accelerator
- Scratch PAD memory with 3 banks of30 x 32-bit registers
- 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
- 1 interrupt controller (INTC), minimum of 64 input events supported
High-Speed Interfaces:
- Integrated Ethernet switch
supporting(total of 2 external ports)
- RMII(10/100) or RGMII (10/100/1000)
- IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
- Clause 45 MDIO PHY management
- Packet Classifier based on ALE engine with 512 classifiers
- Priority based flow control
- Time sensitive networking (TSN) support
- Four CPU H/W interrupt Pacing
- IP/UDP/TCP checksum offload in hardware
- Two USB2.0 Ports
- Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
- Integrated USB VBUS detection
General Connectivity:
- 9x Universal Asynchronous Receiver-Transmitters (UART)
- 5x Serial Peripheral Interface (SPI) controllers
- 6x Inter-Integrated Circuit (I2C) ports
- 3x Multichannel Audio Serial
Ports (McASP)
- Transmit and Receive Clocks up to 50 MHz
- Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
- FIFO Buffers for Transmit and Receive(256 Bytes)
- Support for audio reference output clock
- 3x enhanced PWM modules (ePWM)
- 3x enhanced Quadrature Encoder Pulse modules (eQEP)
- 3x enhanced Capture modules (eCAP)
- General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
- 3x Controller Area Network (CAN)
modules with CAN-FD support
- Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
- Full CAN FD support (up to 64 data bytes)
- Parity/ECC check for Message RAM
- Speed up to 8Mbps
Media and Data Storage:
- 3x Multi-Media Card/Secure Digital(MMC/SD/SDIO) interface
- 1x 8-bit eMMC interface up to HS200 speed
- 2x 4-bit SD/SDIO interface up to UHS-I
- Compliant with eMMC 5.1, SD 3.0 andSDIO Version 3.0
- 1× General-Purpose Memory
Controller (GPMC) up to 133 MHz
- Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
- Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module
(ELM)
- Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
- Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
- OSPI/QSPI with DDR / SDR
support
- Support for Serial NAND and Serial NOR flash devices
- 4GBytes memory address support
- XIP mode with optional on-the-fly encryption
Power Management:
- Low power modes supported by
Device/Power Manager
- Partial IO support for CAN/GPIO/UART wakeup
- DeepSleep
- MCU Only
- Standby
- Dynamic frequency scaling for Cortex-A53
Optimal Power Management Solution:
- Recommended TPS65219 Power Management ICs (PMIC)
- Companion PMIC specially designed to meet device power supply requirements
- Flexible mapping and factory programmed configurations to support different use cases
Boot Options:
- UART
- I2C EEPROM
- OSPI/QSPI Flash
- GPMC NOR/NAND Flash
- Serial NAND Flash
- SD Card
- eMMC
- USB (host) boot from Mass Storage device
- USB (device) boot from external host (DFU mode)
- Ethernet
Technology / Package:
- 16-nm technology
- 13mm x 13mm, 0.5-mm pitch, 425-pinFCCSP BGA (AMK)
AM625SIP is a System In Package (SIP) derivative of the ALW packaged AM6254 device, with the addition of an integrated LPDDR4 SDRAM. This document only defines differences or exceptions to the ALW packaged AM6254 device defined in AM62x Sitara Processors Datasheet (revision B or later).
The AM625SIP (System in Package) Sitara™ MPU with integrated LPDDR4 is an application processor built for Linux development. The system in package integrates 512MB of LPDDR4 with the AM6254 device which has 4x Arm® Cortex®-A53 performance and embedded features, such as: dual-display support, 3D graphics acceleration, along with an extensive set of peripherals that make the System in package well-suited for a broad range of industrial applications while offering intelligent features and optimized power architecture. Additionally, the AM625SIP offers a simplified hardware design, increased robustness, optimized size/system BOM, and power consumption savings all enabling faster software and hardware development.
Some of these applications include:
- Industrial HMI
- Medical equipment, Patient monitoring, and Portable medical devices
- Smart home gateways & Appliances
- Embedded security: Control & Access panels
The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM625SIP enables system-level connectivity, such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM625SIP device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications
技術文件
設計與開發
電源供應解決方案
為 AM625SIP 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。
SK-AM62-SIP — 適用於 Sitara™ 處理器的 AM62x 系統級封裝入門套件
SK-AM62-SIP 入門套件 (SK) 評估模組 (EVM) 是以 AM6254 系統單晶片 (SoC) 為建置基礎的獨立測試與開發平台，並在單一封裝中整合 512 MB LPDDR4 SDRAM。AM625SIP 處理器包含四核心 64 位元 ARM®-Cortex®-A53 微處理器與單核心 ARM Cortex-M4F MCU。
SK-AM62-SIP 包括高安全性現場安全 (HS-FS) 矽，可針對安全應用選擇自訂金鑰和加密。
SK-AM62-SIP 讓使用者能夠透過高畫質多媒體介面 (HDMI) [透過每吋點數 (DPI)] 和低壓差分訊號 (...)
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德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別，適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列，可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。同時，所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。 對於針腳上的核心追蹤，則需要 XDS560v2 PRO TRACE。
德州儀器 XDS110 透過 TI 20 針腳連接器（具有用於 TI 14 針腳和 Arm 10 針腳和 Arm 20 針腳的多轉接器）連接到目標電路板，並透過 USB2.0 (...)
TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器
The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)
LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統
Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)
TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger
TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)
MCU-PLUS-SDK-AM62X — MCU+ SDK for AM62x – RTOS, No-RTOS
AM62 處理器 Linux® 軟體開發套件 (SDK) 是用於嵌入式處理器的統合軟體平台，可提供簡易設定，以及可迅速立即利用的基準測試與示範。
此 SDK 的所有版本在 TI 為其提供的廣泛產品組合中都是一致的，開發人員能順暢地在其他產品上重複使用軟體，並開發軟體。
PROCESSOR-SDK-LINUX-AM62X — Processor SDK Linux for AM62x
AM62 處理器 Linux® 軟體開發套件 (SDK) 是用於嵌入式處理器的統合軟體平台，可提供簡易設定，以及可迅速立即利用的基準測試與示範。
此 SDK 的所有版本在 TI 為其提供的廣泛產品組合中都是一致的，開發人員能順暢地在其他產品上重複使用軟體，並開發軟體。
PROCESSOR-SDK-LINUX-RT-AM62X — Processor SDK RT-Linux for AM62x
AM62 處理器 Linux® 軟體開發套件 (SDK) 是用於嵌入式處理器的統合軟體平台，可提供簡易設定，以及可迅速立即利用的基準測試與示範。
此 SDK 的所有版本在 TI 為其提供的廣泛產品組合中都是一致的，開發人員能順暢地在其他產品上重複使用軟體，並開發軟體。
CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)
CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)
DDR-CONFIG-AM62 — DDR Configuration Tool
EDGE-AI-STUDIO — Edge AI Studio
Edge AI Studio 是一系列圖形和命令行工具，旨在加速 TI 處理器、微控制器和雷達感測器上的邊緣 AI 開發。不管是使用來自 TI Model Zoo 的模型，還是
運用您自己的模型來開發概念驗證，Edge AI Studio 都能提供您所需的工具。
Edge AI Studio 圖形使用者介面提供完全整合的解決方案，用於收集和註釋資料、訓練和編譯模型，以在即時開發平台上部署。從 TI Model Zoo 中的各種預先訓練的模型中選擇，並可選擇透過自訂資料重新訓練，以提升準確度和性能。Edge AI Studio (...)
K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs
PRU-CQKIT — TI PRU safety compiler qualification kit (leverages compiler release validations)
開發安全編譯器資格認證套件是為了協助客戶對 TI ARM、C6000、C7000 或 C2000/CLA C/C++ 編譯器的使用進行認證，以確保符合功能安全標準，如 IEC 61508 和 ISO 26262。
安全編譯器資格認證套件：
- 對 TI 客戶免費
- 不需要使用者進行資格測試
- 支援編譯器覆蓋範圍分析
- 覆蓋範圍資料收集的說明可從每個 QKIT 下載頁面下載。
- 不包括 Validas 諮詢
如需存取安全編譯器資格認證套件，請按一下上面其中一個索取按鈕。
如需進一步了解功能安全產品，請造訪 (...)
SYSCONFIG — Standalone desktop version of SysConfig
CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.
SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)
TSK-3P-VX-TOOLSET — 適用於 Arm 的 TASKING VX 工具套件
適用於 Arm 的 VX 工具套件是一套經過認證的編譯器工具鏈，可用於指定 Cortex-M 與 Cortex-R 核心裝置的安全關鍵嵌入式軟體開發。透過整合 Eclipse IDE、進階多核心支援，以及與 TASKING BlueBox 除錯器的相容性，VX 工具套件可簡化開發流程。通過 TÜV NORD 認證，符合 ISO 26262（最高支援 ASIL D）及 ISO 21434 標準。
AM62-ACADEMY — AM62x Academy
TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud
GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS
GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS
The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 預先認證的安全 RTOS
SAFERTOS® 是專為嵌入式處理器設計的獨特即時作業系統。經 TÜV SÜD 預先認證，符合 IEC 61508 SIL3 與 ISO 26262 ASILD 標準。SAFERTOS® 是由 WHIS 專家團隊專為安全而打造，適用於全球重要安全應用。WHIS 與德州儀器的合作已經超過十年。在此期間，WHIS 已將 SAFERTOS® 移植至各種 TI 處理器，支援所有熱門核心，並可依要求提供其他架構。SAFERTOS® 專為您的特定處理器/編譯器組合量身打造，隨附完整的原始程式碼與設計保證包，可完全一目了然整個設計生命週期。許多 WHIS 客戶開始使用 FreeRTOS (...)
DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AMK) | 425 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。