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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

AMIC110

現行

Sitara 處理器：ARM Cortex-A8、10+ 乙太網路通訊協定

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產品規格表
勘誤表

AMIC110

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A8 Frequency (MHz) 300 Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit Features Networking Rating Catalog Power supply solution TPS650250, TPS65216 Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 300 Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit Features Networking Rating Catalog Power supply solution TPS650250, TPS65216 Operating temperature range (°C) -40 to 105
NFBGA (ZCZ) 324 225 mm² 15 x 15
  • Up to 300-MHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock (1))
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX](1), Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Package:
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

(1)The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.
  • Up to 300-MHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock (1))
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX](1), Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Package:
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

(1)The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.

The AMIC110 device is a multiprotocol programmable industrial communications processor providing ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface options. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AMIC110 device is a multiprotocol programmable industrial communications processor providing ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface options. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

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AMIC120 現行 Sitara 處理器；Arm Cortex-A9；超過 10 項乙太網路協定、編碼器協定 AMIC120 includes protocols as AMIC 110 but is a higher performance Cortex - A9 processor with encoder protocols & cryptography

技術文件

star =TI 所選的此產品重要文件
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重要文件 類型 標題 格式選項 日期
* Data sheet AMIC110 Sitara™ SoC datasheet (Rev. D) PDF | HTML 2019年 12月 12日
* Errata AMIC110 Sitara SoC Silicon Errata (Rev. 2.1) 2017年 1月 3日
White paper TI Sitara™ 處理器中的 PROFINET® (Rev. E) PDF | HTML 2026年 4月 20日
White paper TI Sitara™ 프로세서의 PROFINET® (Rev. E) PDF | HTML 2026年 4月 17日
White paper PROFINET on TI’s Sitara™ processors (Rev. E) 2026年 4月 13日
Application note Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 2025年 9月 3日
Technical article How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory PDF | HTML 2020年 8月 24日
White paper EtherCAT® on Sitara™ Processors (Rev. I) 2020年 7月 28日
White paper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020年 7月 28日
E-book E-book: An engineer’s guide to industrial robot designs 2020年 2月 12日
User guide AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 2019年 12月 13日
Application note AM335x EMIF Tools 2019年 9月 20日
User guide Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 2019年 4月 11日
White paper Ensuring real-time predictability (Rev. B) 2018年 12月 4日
Application note PRU-ICSS EtherCAT Slave Troubleshooting Guide 2018年 11月 7日
White paper An inside look at industrial Ethernet communication protocols (Rev. B) 2018年 8月 1日
User guide Powering the AM335x With the TPS650250 (Rev. B) 2018年 3月 14日
Technical article Delivering power to the industrial market with Ethernet PDF | HTML 2018年 3月 8日
Technical article EtherCAT connectivity without DDR PDF | HTML 2018年 1月 30日
Technical article Real-time control meets real-time industrial communications development – part two PDF | HTML 2017年 12月 13日
Technical article New industrial Ethernet protocol: CC-Link IE Field Basic PDF | HTML 2017年 9月 29日
Technical article Reducing factory downtime with predictive maintenance for industrial Ethernet PDF | HTML 2017年 9月 7日
White paper Connected sensors in industrial automation (Rev. B) 2017年 6月 22日
Technical article Making industrial communication easy with AMIC110 SoCs PDF | HTML 2017年 6月 6日
Technical article How to select the right industrial Ethernet standard: PROFIBUS PDF | HTML 2016年 9月 27日
Technical article Start designing your next Sitara™ processor solution! PDF | HTML 2016年 7月 28日
Technical article Expanding industrial communication development PDF | HTML 2016年 5月 9日

設計與開發

電源供應解決方案

為 AMIC110 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

檢視解決方案
開發板

TMDXICE110 — AMIC110 工業通訊引擎 (ICE)

AMIC110 工業通訊引擎 (ICE) 是一款專為工業通訊，特別是工業乙太網路所設計的開發平台。AMIC110 ICE 的關鍵在於 Sitara AMIC110 SoC，此 SoC 配備 Arm® Cortex™-A8 處理器，以及可編程即時單元工業通訊子系統 (PRU-ICSS)，可整合即時工業通訊協定，無需 ASIC 或 FPGA。AMIC110 ICE 採用 BoosterPack™ 插入式模組外型尺寸，可搭配 C2000 LaunchPad™ 開發套件使用，用於開發連接馬達驅動器的解決方案，以及工廠自動化中的工業感測器和 IO。

使用指南: PDF
TI.com 無法提供
開發板

CRLNK-3P-SOMS — 適用於 TI ARM 架構處理器的 Critical Link MitySOM 系統模組

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

從：Critical Link LLC
造訪合作夥伴網站
開發板

VANWS-3P-VGATEWAY — 來自基於 AM335x 的 Vanteon 無線解決方案的 vGATEWAY 參考設計

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

從：Vanteon Wireless Solutions
造訪合作夥伴網站
偵錯探測器

TMDSEMU110-U — XDS110 JTAG 偵錯探測器

德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別，適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列，可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。同時，所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。  對於針腳上的核心追蹤，則需要 XDS560v2 PRO TRACE。

德州儀器 XDS110 透過 TI 20 針腳連接器（具有用於 TI 14 針腳和 Arm 10 針腳和 Arm 20 針腳的多轉接器）連接到目標電路板，並透過 USB2.0 (...)

使用指南: PDF
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偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-AMIC110 — 適用於 AMIC110 Sitara 處理器的處理器 SDK – 支援 TI-RTOS

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。  所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。  有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。
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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AM335X — TI-RTOS Processor SDK for AM335x and AMIC110 devices (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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驅動程式或資料庫

PRU-ICSS-ETHERCAT-SLAVE — PRU-ICSS software for EtherCAT slave

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors.  The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)

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驅動程式或資料庫

PRU-ICSS-ETHERNETIP-ADAPTER — PRU-ICSS software for EtherNetIP adapter

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors.  The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)

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驅動程式或資料庫

PRU-ICSS-HSR-PRP-DAN — PRU-ICSS software for HSR/PRP

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors.  The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)

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驅動程式或資料庫

PRU-ICSS-PROFIBUS-SLAVE — PRU-ICSS software for PROFIBUS slave

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors.  The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)

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驅動程式或資料庫

PRU-ICSS-PROFINET-SLAVE — PRU-ICSS software for Profinet slave

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors.  The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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線上培訓

BOOTL-3P-TRAINING — 適用於 TI Arm 架構處理器的嵌入式軟體開發訓練

從：Bootlin
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軟體程式設計工具

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)

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軟體程式設計工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash is part of TI's extensive CCStudio™ development ecosystem and is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces and can be run on (...)

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模擬型號

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS Model
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模擬型號

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL Model
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組裝圖

AMIC110 ICE Design Files

SPRR280.ZIP (10806 KB)
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物料清單

AMIC110 ICE Bill of Materials

SPRR279.PDF (91 KB)
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
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計算工具

POWEREST — 功率估計工具 (PET)

功耗估算工具 (PET) 讓使用者能深入瞭解特定 TI 處理器的功耗情況。本工具允許使用者選擇多種應用場景，不僅能掌握功耗數據，更能理解如何運用進階節能技術進一步降低整體功耗。
AM57x 與 AM437x 處理器專用 PET：

此可下載試算表提供使用者輸入應用所需裝置參數的機制。參數包含 IP 模組活動狀態/負載量、目標電源模式及電源管理使用情境。可設定多重運作條件並為每種狀態配置時間區段。電源估算數據已內嵌於試算表中，所有結果將直接在試算表內自動生成（無需上傳任何資料）。

AM57x 專用 PET：

(...)

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PCB 佈局

AMIC110 ICE Bottom Assembly Files

SPRR276.PDF (636 KB)
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PCB 佈局

AMIC110 ICE Top Assembly Files

SPRR277.PDF (629 KB)
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配置圖

AMIC110 ICE Schematic Files

SPRR278.ZIP (1897 KB)
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參考設計

TIDEP0008 — PROFINET 通訊開發平台

Targeted for PROFINET secondary communications, this reference design helps you implement PROFINET communications standards in a broad range of industrial automation equipment. It enables low-footprint designs in applications such as industrial automation, factory automation or (...)
使用指南: PDF
電路圖: PDF
參考設計

TIDEP0029 — 具有 1 GHz ARM 應用處理器的認證 Profinet IRT V2.3 裝置

此參考設計將工業乙太網路 Phys、Profinet IRT 交換器、Profinet IRT 堆疊及應用範例整合在單一封裝中。Profinet 是許多工業領域和終端設備所使用的主要工業乙太網路標準，這些領域和終端設備需要即時決定性的 IO 資料交換，以及用於服務與診斷的額外頻寬。此設計包含 TMDSICE3359，但可支援 TMDXICE110。
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0003 — 乙太網路/IP 通訊開發平台

Targeted for Ethernet/IP secondary communications, this development platform allows you to implement Ethernet/IP communication standards in a broad range of industrial automation equipment. It enables low footprint designs in applications such as industrial automation, factory automation or (...)
電路圖: PDF
參考設計

TIDEP0002 — PROFIBUS 通訊開發平台

Targeted for PROFIBUS slave communications, this development platform allows designers to implement PROFIBUS communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or (...)
電路圖: PDF
參考設計

TIDA-00299 — EtherCAT 從屬設備和多協定工業乙太網路參考設計

此參考設計採用高 EMC 抗擾度且經過成本最佳化的 EtherCAT 從屬裝置（雙連接埠），並透過 SPI 介面連接至應用處理器。此硬體設計採用 AMIC110 工業通訊處理器，能支援多種協定的工業乙太網路與現場匯流排。此設計僅需單一 5V 電源供應，並由 PMIC 產生所有必要的板載電源軌。EtherCAT 從屬協定堆疊可透過序列周邊介面 (SPI) 在 AMIC110 或應用處理器上執行。透過硬體開關，AMIC110 可設定為從 SPI 快閃記憶體啟動 EtherCAT 從屬韌體，或透過 SPI 由應用處理器啟動。此設計已搭配執行 EtherCAT 主站的標準工業 PLC 進行 (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP-0105 — AMIC110 上的無 DDR EtherCAT® 從屬設備參考設計

EtherCAT®（控制自動化技術乙太網路）持續成長，成為主流工業乙太網路。無 DDR EtherCAT 參考設計可做為在 AMIC110 多協定工業單晶片 (SoC) 通訊系統上，使用全新的低成本無 DDR EtherCAT 從屬設備的參考設計。此參考設計展示了完全在 SoC 內部記憶體中執行完整 EtherCAT 從屬堆疊的能力。此參考設計省去外部 ASIC 和 DDR，可大幅節省系統物料清單 (BOM) 相關成本和電路板空間。  此外，由於省去 EtherCAT 的外部記憶體傳輸，從而實現了更快的傳輸速度，這使得連線工業驅動和通訊模組等應用的性能得以大幅提升。
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0049 — 適用於 AM335x 的工業乙太網路「快速啟動」功能

此參考設計為 Sitara 處理器上的整合式多通訊協定工業乙太網路通訊。依各種工業乙太網路標準定義將裝置開機後，即可快速啟動。此參考設計說明能夠以 Sitara 處理器快速啟動的系統級方法。該設計使用了 TMDSICE3359，但也可使用 TMDXICE110。
Design guide: PDF
電路圖: PDF
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