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Product details

Parameters

VO (V) 2.5 Initial accuracy (Max) (%) 0.05 Temp coeff (Max) (ppm/ degree C) 5 Rating Catalog Vin (Min) (V) 3 Vin (Max) (V) 5.5 Iq (Typ) (uA) 820 Features Integrated Low Output Impedance Buffer Iout/Iz (Max) (mA) 4 Operating temperature range (C) -40 to 125 Shutdown current (Typ) (uA) 1 open-in-new Find other Series voltage references

Package | Pins | Size

VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other Series voltage references

Features

  • Excellent Temperature Drift Performance
    • 5 ppm/°C (max) from –40°C to +125°C
  • Extremely Low Noise
    • Total Noise: 5 µVRMS With 47-µF Capacitor
    • 1/f Noise (0.1 Hz to 10 Hz): 3 µVPP/V
  • Integrated ADC Drive Buffer
    • Low Output Impedance: < 50 mΩ (0-200 kHz)
    • First Sample Precise to 18 Bits With ADS8881
    • Enables Burst-Mode DAQ Systems
  • Low Supply Current: 820 µA
  • Low Shutdown Current: 1 µA
  • High Initial Accuracy: ±0.05%
  • Very-Low Noise and Distortion
    • SNR: 100.5 dB, THD: –125 dB (ADS8881)
    • SNR: 106 dB, THD: –120 dB (ADS127L01)
  • Output Current Drive: ±4 mA
  • Programmable Short-Circuit Current
  • Verified to Drive REF Pin of ADS88xx family of SAR ADCs and ADS127xx family of Wideband ΔΣ ADCs

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Description

The REF6000 family of voltage references have an integrated low output impedance buffer that enable the user to directly drive the REF pin of precision data converters, while preserving linearity, distortion, and noise performance. Most precision SAR and Delta-Sigma ADCs, switch binary-weighted capacitors onto the REF pin during the conversion process. In order to support this dynamic load the output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The REF6000 family devices are well suited, but not limited, to drive the REF pin of the ADS88xx family of SAR ADCs, and ADS127xx family of delta-sigma ADCs, as well as other digital-to-analog converters (DACs).

The REF6000 family of voltage references are able to maintain an output voltage within 1LSB (18-bit) with minimal droop, even during the first conversion while driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time sampling, and variable-sampling-rate data-acquisition systems. The REF60xx variants of REF6000 family specify a maximum temperature drift of just 5 ppm/°C and initial accuracy of 0.05% for both the voltage reference and the low output impedance buffer combined. For various temperature drift options in REF6000 family, see the Device Comparison Table.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet REF60xx High-Precision Voltage Reference With Integrated ADC Drive Buffer datasheet (Rev. B) Aug. 29, 2016
Application notes Expanding Analog Input Channels in Grid Applications (Using 16-Channel, 16-Bit, Jun. 15, 2020
White papers Voltage Supervisor and Reset ICs: Tips, Tricks and Basics Jun. 28, 2019
White papers Tips and tricks for designing with voltage references May 30, 2017
Technical articles Why is it so challenging to design a voltage reference circuit for an ADC? Sep. 16, 2016
White papers Voltage-reference impact on total harmonic distortion Aug. 01, 2016
User guides REF6025EVM-PDK User Guide May 19, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADS127L01EVM is an evaluation platform for the ADS127L01. The ADS127L01 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with data rates up to 512 kSPS. It offers a unique combination of excellent dc accuracy and outstanding ac perforamnce. The high-order, chopper-stabilized modulator (...)

Features
  • Includes all require support circuitry for the ADS127L01
  • Enhanced evaluation software enables quicker configuration and analysis
  • Configurable inputs, references, supplies and clock sources
  • Easily accessible signals via testpoints and headers
EVALUATION BOARDS Download
document-generic User guide
Description

The ADS7066 evaluation module (EVM) performance demonstration kit (PDK) is a platform for evaluating the performance of the ADS7066 successive approximation register (SAR) analog-to-digital converter (ADC)

The ADS7066EVM-PDK provides power and a communications card complete with a graphical user (...)

Features
  • Hardware and software required for diagnostic testing, as well as accurate performance evaluation of ADS7066 SAR ADC
  • USB powered; no external power supply required
  • Includes precision ADC motherboard (PAMBoard) development kit that provides a convenient communication interface over a USB for power (...)
EVALUATION BOARDS Download
document-generic User guide
149
Description
The ADS8881EVMV2-PDK is an evaluation platform for the ADS8881 successive approximation register (SAR) analog-to-digital converter (ADC). The evaluation kit includes the ADS8881 EVMV2 board, the PHI controller board, and accompanying computer software that enables the user to communicate with (...)
Features
  • Includes hardware and software required for diagnostic testing, as well as accurate performance evaluation of the ADS8881 ADC
  • No external power supply needed
  • Ships with PHI EVM controller, which provides convenient interface to the EVM over USB 2.0 (or higher) for power delivery and digital interface
  • (...)
EVALUATION BOARDS Download
document-generic User guide
149
Description
The REF6025EVM-PDK is a platform for evaluating the performance of the REF6025 voltage reference. The evaluation kit brings out the burst mode performance of the device which is a key feature of the device.
Features
  • TI’s first ultra-high precision reference
  • Introduces ADC drive buffer which is an integrated high bandwidth, output impedance buffer that helps achieve the lowest distortion, ultra-low-noise data acquisition systems
  • Introduces burst mode data acquisition with first-sample correct to 18-bit (...)

Design tools & simulation

SIMULATION MODELS Download
SBOM984.ZIP (31 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SBOM985.TSC (6483 KB) - TINA-TI Reference Design
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

REFERENCE DESIGNS Download
Universal data concentrator reference design supporting Ethernet, 6LoWPAN RF mesh and more
TIDA-010032 — IPv6-based grid communications are becoming the standard choice in industrial markets and applications like smart meters and grid automation. The universal data concentrator design provides a complete IPv6-based network solution integrated with Ethernet backbone communication, 6LoWPAN RF mesh (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
IEPE Vibration Sensor Interface for PLC Analog Input Reference Design
TIDA-01471 — Industrial vibration sensing is crucial part in condition monitoring necessary for predictive maintenance. Integrated Electronic Piezoelectric (IEPE) sensor is the most common vibration sensor used in industrial environment. This design is a full analog front-end for IEPE sensor interface (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
16 bit 1MSPS Data Acquisition Reference Design for Single-Ended Multiplexed Applications
TIPD173 This TI Precision Verified Design details a systematic design methodology for a 16 bit, 1MSPS, single-ended data acquisition (DAQ) block optimized to achieve excellent settling time, power consumption, static performance and dynamic performance for multiplexed applications.  The design features (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VSSOP (DGK) 8 View options

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