Low-Power, 14-Bit, 1-MHz, Single Unipolar Input, ADC with Serial Interface
Product details
Parameters
Package | Pins | Size
Features
- 2.7V to 5.5V Analog Supply, Low Power:
- 13.7mW (1MHz, +VA = 3V, +VBD = 1.8V)
- 1MHz Sampling Rate 3V ≤ +VA ≤ 5.5V,
900kHz Sampling Rate 2.7V ≤ +VA ≤ 3V - Excellent DC Performance:
- ±0.4LSB Typ, ±1.0LSB Max INL
- ±0.4LSB Typ, ±1.0LSB Max DNL
- ±0.8mV Max Offset Error at 3V
- ±1.25mV Max Offset Error at 5V
- Excellent AC Performance at fi = 10kHz with 85.9dB SNR, 105.3dB SFDR, -100.1dB THD
- Built-In Conversion Clock (CCLK)
- 1.65V to 5.5V I/O Supply:
- SPI/DSP-Compatible Serial Interface
- SCLK up to 50MHz
- Comprehensive Power-Down Modes:
- Deep Power-Down
- Nap Power-Down
- Auto Nap Power-Down
- Unipolar Input Range: 0V to VREF
- Software Reset
- Global CONVST (Independent of CS)
- Programmable Status/Polarity EOC/INT
- 4 × 4 QFN-16 and TSSOP-16 Packages
- Multi-Chip Daisy-Chain Mode
- Programmable TAG Bit Output
- Auto/Manual Channel Select Mode (ADS7280)
- APPLICATIONS
- Communications
- Transducer Interface
- Medical Instruments
- Magnetometers
- Industrial Process Control
- Data Acquisition Systems
- Automatic Test Equipment
Description
The ADS7279 is a low-power, 14-bit, 1MSPS analog-to-digital converter (ADC) with a unipolar input. The device includes a 14-bit, capacitor-based successive approximation register (SAR) ADC with inherent sample-and-hold.
The ADS7280 is based on the same core and includes a 2-to-1 input MUX with a programmable TAG bit output option. Both the ADS7279 and ADS7280 offer a high-speed, wide voltage serial interface, and are capable of daisy-chain mode operation when multiple converters are used.
These converters are available in 4 × 4 QFN and TSSOP-16 packages, and are fully specified for operation over the industrial -40°C to +85°C temperature range.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | LOW-POWER, 14-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ADC w/SERIAL INTERFACE datasheet (Rev. A) | Jun. 17, 2009 |
E-book | Best of Baker's Best: Precision Data Converters -- SAR ADCs | May 21, 2015 | |
Application note | Determining Minimum Acquisition Times for SAR ADCs, part 2 | Mar. 17, 2011 | |
Application note | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | Nov. 10, 2010 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Features
- Expedites circuit design with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)
- Noise calculations
- Common unit translation
- Solves common amplifier circuit design problems
- Gain selections using standard resistors
- Filter configurations
- Total noise for common amplifier configurations
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
QFN (RSA) | 16 | View options |
TSSOP (PW) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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