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LMK61E2

ACTIVE

156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

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Data sheet

LMK61E2

ACTIVE
Data sheet Order now

Product details

Features Programmable frequency Output frequency (MHz) 1000 Output type HCSL, LVDS, LVPECL Stability (ppm) 50 Supply voltage (V) 3.3 Jitter (ps) 0.1 Operating temperature range (°C) -40 to 85 Rating Catalog
Features Programmable frequency Output frequency (MHz) 1000 Output type HCSL, LVDS, LVPECL Stability (ppm) 50 Supply voltage (V) 3.3 Jitter (ps) 0.1 Operating temperature range (°C) -40 to 85 Rating Catalog
QFM (SIA) 8 12.25 mm² 3.5 x 3.5
  • Ultra-Low Noise, High Performance
    • Jitter: 90 fs RMS Typical fOUT > 100 MHz
    • PSRR: –70 dBc, Robust Supply Noise Immunity
  • Flexible Output Format; User Selectable
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±50 ppm
  • System Level Features
    • Frequency Margining: Fine and Coarse
    • Internal EEPROM: User Configurable Default Settings
  • Other Features
    • Device Control: I2C
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
    • Create a Custom Design Using the LMK61E2 With the WEBENCH® Power Designer
  • Ultra-Low Noise, High Performance
    • Jitter: 90 fs RMS Typical fOUT > 100 MHz
    • PSRR: –70 dBc, Robust Supply Noise Immunity
  • Flexible Output Format; User Selectable
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±50 ppm
  • System Level Features
    • Frequency Margining: Fine and Coarse
    • Internal EEPROM: User Configurable Default Settings
  • Other Features
    • Device Control: I2C
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
    • Create a Custom Design Using the LMK61E2 With the WEBENCH® Power Designer

The LMK61E2 device is an ultra-low jitter PLLatinum programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.

The device features self start-up from on-chip EEPROM that is factory programmed to generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable in-system through I2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ± 5% supply.

The device provides fine and coarse frequency margining options through I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.

The LMK61E2 device is an ultra-low jitter PLLatinum programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.

The device features self start-up from on-chip EEPROM that is factory programmed to generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable in-system through I2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ± 5% supply.

The device provides fine and coarse frequency margining options through I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.
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Technical documentation

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Type Title Date
* Data sheet LMK61E2 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet (Rev. B) PDF | HTML 03 Feb 2017
Technical article Clock tree fundamentals: finding the right clocking devices for your design PDF | HTML 24 Mar 2021
Application note Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML 30 Sep 2020
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML 04 Jun 2019
Technical article Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy PDF | HTML 28 Aug 2017
EVM User's guide LMK61E2EVM, LMK61E0MEVM User's Guide (Rev. B) 10 Aug 2017
Application note Vibration and Shock Sensitivity: A Comparative Study of Oscillators 11 Jan 2017
Technical article Complete clock-tree solutions that make a hardware designer’s life easier PDF | HTML 10 Mar 2016
Technical article How to select an optimal clocking solution for your FPGA-based design PDF | HTML 09 Dec 2015
Application note Time Domain Jitter Measurement Consideration for Low-Noise Oscillators PDF | HTML 05 Oct 2015
Application note Frequency Margining Using TI's High Performance Programmable Oscillators 02 Oct 2015

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