SPRUJ55 User guide

SPRUJ55D September 2023 – July 2025 AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

3.1 System Interconnect Overview

The device implements a system interconnect using TI’s Common Bus Architecture (CBA), composed of the VBUSM and VBUSP protocols.

The system is based on a multi-layered interconnect approach designed to meet high-performance system requirements. The core interconnect structure consists of a full crossbar implementation, where every initiator has an independent communication path with every target. In other words, any initiator can access any target on the interconnect while another initiator can access a different target simultaneously without any contention,such that, transactions from each initiator has access to full interconnect bandwidth. Arbitration will only happen at the target end point (when the same target is accessed by two or more initiators) with round-robin prioritization. Targets cannot generate read/write requests directly. However, they can respond to these requests by generating error events (as defined by the CBA protocol), interrupts, and DMA requests.

The device interconnect is partitioned into the following sections:

CORE VBUSM Interconnect
CORE VBUSP Interconnect
R5SS0 VBUSM Interconnect
R5SS1 VBUSM Interconnect
PERI VBUSP Interconnect
INFRA0 VBUSP Interconnect
INFRA1 VBUSP Interconnect
R5SS0 CONFIG TARGET Interconnect
R5SS1 CONFIG TARGET Interconnect
CONTROLSS VBUSP Interconnect

AM263Px

Figure 3-1 Top-Level System Interconnect

Note:

CORE VBUSM, R5SS0 VBUSM and R5SS1 VBUSM Interconnects are 64-bit wide interconnect (i.e. 64-bit data bus width). Rest of the above interconnects are 32-bit wide (i.e. 32-bit data bus width).

There are multiple targets for each of the above interconnects, these are detailed in later sections of the chapter.