SPRUJ55 User guide

SPRUJ55D September 2023 – July 2025 AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

3.9 CONTROLSS Interconnect

CONTROLSS interconnect is divided into below list of separate interconnect connected to the CORE VBUSP interconnect individually. Since these are connected to the CORE VBUSP interconnect separately, each of this interconnect can be accessed in parallel by different initiators without any arbitration. Accessing a single CONTROLSS interconnect by multiple initiators at the same time will be arbitrated.

MISC PERIPH
MISC CONFIG0
MISC CONFIG1
SC_FSI0 (FSITX[0:1] and FSIRX[0:1])
SCR_FSI1 (FSITX[2:3] and FSIRX[2:3])
G0_EPWM, G1_EPWM, G2_EPWM, G3_EPWM
ADC0, ADC1, ADC2, ADC3, ADC4, ADC5
MISC PERIPH, MISC CONFIG0, MISC CONFIG1, SCR_FSI0 and SCR_FSI1 are single initiator, multiple targets as shown in the diagram.

EPWM interconnect are divided into 4 groups G0_EPWM, G1_EPWM, G2_EPWM and G3_EPWM accessed using different address regions in the memory map. Any initiator can access an EPWM group while another initiator is accessing a different EPWM group simultaneously. Each interconnect has n target ports depending on number of EPWM in the design. After the interconnect, a 4:1 Static Mux can be configured per EPWM using CONTROLSS_GLOBAL_CTRL.EPWM_STATICXBAR_SEL0 & CONTROLSS_GLOBAL_CTRL.EPWM_STATICXBAR_SEL1 register, which statically assigns that EPWM to any of the selection groups – G0 to G3.
Additionally, for each EPWM group, there is a 4KB write only alias region added in the device memory map ( CONTROLSS_G0_EPWM_WLINK to CONTROLSS_G3_EPWM_WLINK), using which selected EPWM instances of that particular group can be written together in a single write. The registers CONTROLSS_GLOBAL_CTRL.CONTROLSS_G0_EPWM_WLINK to CONTROLSS_GLOBAL_CTRL.CONTROLSS_G3_EPWM_WLINK contains EPWM enables to select which instances can be written together.

SCR_ADC0, SCR_ADC1,.. SCR_ADCn are different interconnect per intiator (R5FSS0-0_AHB, R5FSS0-1_AHB,R5FSS1-0_AHB, R5FSS1-1_AHB, CORE VBUSP (Port0), and CORE VBUSP (Port1)). The target ports are based on number of ADCs in the design. Each initiator can independently access any ADC register without any arbitration. In other words, the same ADC result register can be accessed by multiple initiators simultaneously without contention.