The processor which wishes to send a message to another processor writes the message to the mailbox memory space, then interrupts the receiver processor. The receiver processor acknowledges the interrupt, then reads the message from the mailbox memory space. The receiver informs the sender that the message is read by an interrupt, which is acknowledged back by the sender. The sender must not initiate another message to the same receiver until the previously initiated mailbox interaction with the same receiver is complete.
The following sequence is followed for performing a mailbox communication.
- SENDER Processor writes the message in a shared SRAM space accessible by the
RECEIVER Processor.
- SENDER Processor triggers an interrupt to RECEIVER by writing 1 to
<SENDER>_MBOX_WRITE_DONE[RECEIVER].
- RECEIVER Processor gets a single aggregated interrupt “MBOX_READ_REQ” for all
interprocessor communication from all senders.
- RECEIVER Processor reads the register <RECEIVER>_MBOX_READ_REQ and sees bit
[SENDER] is set to 0x1.
- RECEIVER Processor writes 0x1 to <RECEIVER>_MBOX_READ_REQ[SENDER] to clear
the interrupt.
- RECEIVER Processor reads the message from shared memory.
- RECEIVER Processor generates an acknowledge interrupt to SENDER Processor by
writing 0x1 to RECEIVER>_MBOX_READ_DONE_ACK[SENDER]
- SENDER Processor gets a single aggregated interrupt “MBOX_READ_DONE” for all
interprocessor communication from all Receivers.
- SENDER Processor reads the register <SENDER>_MBOX_READ_DONE and sees bit
[RECEIVER] is 0x1.
- SENDER Processor writes 0x1 to <SENDER>_MBOX_READ_DONE [RECEIVER] to clear
the interrupt.
Note:
The mailbox scheme ensures the number of mailbox interrupts to a processor is
always only 2, regardless of the number of processors in the SoC.
(MBOX_READ_REQ and MBOX_READ_DONE)
Note:
Every processor is always writing to its own designated mailbox registers.