SPRUJ55D September   2023  â€“ July 2025 AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
      1.      Glossary
      2.      Trademarks
      3.      Export Control Notice
      4.      Related Documentation From Texas Instruments
    2.     Support Resources
    3.     Release History
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Module Allocation and Instances
      1.      AM263Px Register Addendum Link
    4. 1.4 Device Modules
      1. 1.4.1  Arm Cortex-R5F Processor Sub System (R5FSS)
      2. 1.4.2  Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
      3. 1.4.3  Hardware Security Module (HSM)
      4. 1.4.4  Real-time Control Subsystem (CONTROLSS)
      5. 1.4.5  Spinlock (SPINLOCK)
      6. 1.4.6  Enhanced Data Movement Architecture (EDMA)
      7. 1.4.7  General Purpose Input/Output Interface (GPIO)
      8. 1.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 1.4.9  Serial Peripheral Interface (SPI)
      10. 1.4.10 Universal Asynchronous Receiver/Transmitter (UART)
      11. 1.4.11 3-port Gigabit Ethernet Switch (CPSW)
      12. 1.4.12 Octal Serial Peripheral Interface (OSPI)
      13. 1.4.13 Multi-Media Card/Secure Digital Interface (MMCSD)
      14. 1.4.14 Controller Area Network (MCAN)
      15. 1.4.15 Local Interconnect Network (LIN)
      16. 1.4.16 Timers
      17. 1.4.17 Internal Diagnostics Modules
    5. 1.5 Device Identification
  4. 2 Memory Map
    1. 2.1 Device Memory Map
    2. 2.2 R5FSS Memory Map
    3. 2.3 PRU-ICSS Memory Map
  5. 3 System Interconnect
    1. 3.1  System Interconnect Overview
    2. 3.2  CORE VBUSM Interconnect
    3. 3.3  CORE VBUSP Interconnect
    4. 3.4  PERI VBUSP Interconnect
    5. 3.5  INFRA0 VBUSP Interconnect
    6. 3.6  INFRA1 VBUSP Interconnect
    7. 3.7  R5SS0 CONFIG SLV Interconnect
    8. 3.8  R5SS1 CONFIG SLV Interconnect
    9. 3.9  CONTROLSS Interconnect
    10. 3.10 Interconnect Safety
    11. 3.11 Bus Safety Errors
      1. 3.11.1 Error Signaling Integration
      2. 3.11.2 Programming sequence
      3. 3.11.3 Diagnostic Check Mechanism
    12. 3.12 System Memory Protection Unit (MPU)/Firewalls
      1. 3.12.1 MPU Overview
      2. 3.12.2 MPU Instances
      3. 3.12.3 MPU Functional Description
        1. 3.12.3.1 Functional Operation
        2. 3.12.3.2 Protection of the MPU Configuration Registers
        3. 3.12.3.3 MPU Interrupt Requests
      4. 3.12.4 MPU Parameters
      5. 3.12.5 MPU Default HW Configuration
      6. 3.12.6 ISC (Initiator-side Security Control)
        1. 3.12.6.1 ID Allocation
          1. 3.12.6.1.1 64
  6. 4 Module Integration
    1. 4.1  ADC Integration
    2. 4.2  Resolver to Digital Convertor Integration
    3. 4.3  Resolver Integration
    4. 4.4  DAC Integration
    5. 4.5  eCAP Integration
    6. 4.6  EPWM Integration
    7. 4.7  EQEP Integration
    8. 4.8  FSI Integration
    9. 4.9  SDFM Integration
    10. 4.10 SOC_TIMESYNC_XBAR0 Integration
    11. 4.11 SOC_TIMESYNC_XBAR1 Integration
    12. 4.12 GPIO Integration
    13. 4.13 I2C Integration
    14. 4.14 SPI Integration
    15. 4.15 UART Integration
    16. 4.16 CPSW93G Integration
    17. 4.17 MMCSD Integration
    18. 4.18 OSPI Integration
    19. 4.19 MCAN Integration
    20. 4.20 LIN Integration
    21. 4.21 RTI Integration
    22. 4.22 WWDT Integration
    23. 4.23 DCC Integration
    24. 4.24 ESM Integration
    25. 4.25 ECC Aggregator Integration
    26. 4.26 MCRC Integration
    27. 4.27 ICSSM_XBAR_INTROUTER Integration
    28. 4.28 GPIO_XBAR Integration
  7. 5 Initialization
    1. 5.1 Initialization Overview
      1. 5.1.1 ROM Code Overview
      2. 5.1.2 Bootloader Modes
      3. 5.1.3 Boot Terminology
    2. 5.2 Boot Process
      1. 5.2.1 Public ROM Code Architecture
        1. 5.2.1.1 Public ROM Entry
        2. 5.2.1.2 Main Module
        3. 5.2.1.3 Boot Loop
        4. 5.2.1.4 Modules
        5. 5.2.1.5 Drivers
        6. 5.2.1.6 IPC
    3. 5.3 Boot Mode Pins
      1. 5.3.1 BOOTMODE Pin Mapping
    4. 5.4 Boot Modes
      1. 5.4.1 OSPI Boot
        1. 5.4.1.1 OSPI (8S) and xSPI (8D)
          1. 5.4.1.1.1 OSPI (8S) Bootloader Operation
            1. 5.4.1.1.1.1 OSPI (8S) Loading Process
        2. 5.4.1.2 OSPI (8S) and xSPI (8D) - SIP Package
          1. 5.4.1.2.1 OSPI (8S) - Bootloader Operation of SIP Package
            1. 5.4.1.2.1.1 OSPI (8S) - Loading Process of SIP Pacakge
        3. 5.4.1.3 Quad Read (4S)
          1. 5.4.1.3.1 OSPI (4S) Bootloader Operation
            1. 5.4.1.3.1.1 OSPI (4S) Loading Process
        4. 5.4.1.4 OSPI (1S)
          1. 5.4.1.4.1 OSPI (1S) Bootloader Operation
            1. 5.4.1.4.1.1 OSPI (1S) Loading Process
      2. 5.4.2 UART Boot
        1. 5.4.2.1 UART Bootloader Operation
          1. 5.4.2.1.1 Initialization Process
          2. 5.4.2.1.2 UART Loading Process
            1. 5.4.2.1.2.1 UART XMODEM
          3. 5.4.2.1.3 UART Hand-Over Process
      3. 5.4.3 DevBoot
    5. 5.5 Redundant boot support
    6. 5.6 PLL Configuration
    7. 5.7 Secure Boot Flow
      1. 5.7.1 Overview
      2. 5.7.2 x509 Certificate Structure
      3. 5.7.3 Certificate expectations
      4. 5.7.4 Object Identifiers
        1. 5.7.4.1 Boot Information OID (1.3.6.1.4.1.294.1.1)
        2. 5.7.4.2 Software Revision OID (1.3.6.1.4.1.294.1.3)
        3. 5.7.4.3 Image Integrity OID (1.3.6.1.4.1.294.1.2)
        4. 5.7.4.4 Image Encryption OID (1.3.6.1.4.1.294.1.4)
        5. 5.7.4.5 Derivation OID (1.3.6.1.4.1.294.1.5)
        6. 5.7.4.6 Debug OID (1.3.6.1.4.1.294.1.8)
      5. 5.7.5 Binary Image Creation
      6. 5.7.6 Binary Image Verification
      7. 5.7.7 R5 SBL Handoff
      8. 5.7.8 HSM RunTime Handoff
      9. 5.7.9 Post Boot Status
        1. 5.7.9.1 R5
          1. 5.7.9.1.1 Memory
          2. 5.7.9.1.2 Clock
          3. 5.7.9.1.3 IP Blocks
          4. 5.7.9.1.4 Pinmux Settings
          5. 5.7.9.1.5 PBIST
        2. 5.7.9.2 Assets
    8. 5.8 Boot Image Format
      1. 5.8.1 Overall Structure
      2. 5.8.2 Generating X.509 Certificates
        1. 5.8.2.1 Key Generation
          1. 5.8.2.1.1 RSA Key Generation
        2. 5.8.2.2 Configuration Script
        3. 5.8.2.3 Image Data
    9. 5.9 Boot Memory Maps
      1. 5.9.1 Memory Layout/MPU
      2. 5.9.2 Logger
  8. 6 Device Configuration
    1. 6.1 Control Module
      1. 6.1.1 Control Overview
        1. 6.1.1.1 MMR Write Protection
        2. 6.1.1.2 MMR Access Error Interrupt
      2. 6.1.2 TOP_CTRL
        1. 6.1.2.1 TOP_CTRL Integration
      3. 6.1.3 MSS_CTRL
        1. 6.1.3.1 MSS_CTRL Integration
        2. 6.1.3.2 MSS_CTRL Functional Description
          1. 6.1.3.2.1  R5FSS CPU Global Configuration and Control
            1. 6.1.3.2.1.1 R5SS Lock Step/Dual Core Configuration
            2. 6.1.3.2.1.2 R5 Core Halting and Unhalting
            3. 6.1.3.2.1.3 R5 Wait-For-Interrupt (WFI)
          2. 6.1.3.2.2  Memory Initialization
            1. 6.1.3.2.2.1 R5 TCM Memory Initialization
            2. 6.1.3.2.2.2 L2 OCRAM and Mailbox RAM and EDMA RAM Memory Initialization
          3. 6.1.3.2.3  EDMA Configuration
            1. 6.1.3.2.3.1 EDMA Global Configuration and Event Aggregation
            2. 6.1.3.2.3.2 EDMA Error Aggregation
          4. 6.1.3.2.4  CPSW Global Configuration
          5. 6.1.3.2.5  ICSSM Global Configuration
          6. 6.1.3.2.6  MPU Interrupt Aggregator
          7. 6.1.3.2.7  MMR Access Error Interrupt Aggregator
          8. 6.1.3.2.8  Safety Registers
            1. 6.1.3.2.8.1 R5 Memory ECC Error Aggregator
            2. 6.1.3.2.8.2 R5SS TCM Address Parity Error Aggregator
            3. 6.1.3.2.8.3 Interconnect Safety
          9. 6.1.3.2.9  MSS_CTRL MMR Kick Protection Registers
          10. 6.1.3.2.10 MSS_CTRL MMR Access Error Registers
      4. 6.1.4 CONTROLSS_CTRL (CTRLMMR2)
      5. 6.1.5 IOMUX (PADCFG_CTRLMMR0)
      6. 6.1.6 TOPRCM (RCM_CTRLMMR0): SoC-level Clock and Reset control registers
      7. 6.1.7 MSS_RCM (RCM_CTRLMMR1): SoC and Peripheral-level Clock and Reset control registers
    2. 6.2 Power
      1. 6.2.1 Power Management Overview
        1. 6.2.1.1 Using the Device Analog LDO for VPP Supply
      2. 6.2.2 Power Management Unit
        1. 6.2.2.1 PMU Reference System (REFSYS)
        2. 6.2.2.2 PMU Safety System (SAFETYSYS)
          1. 6.2.2.2.1 Power OK (POK) Modules
          2. 6.2.2.2.2 Thermal Manager
            1. 6.2.2.2.2.1 Thermal Manager Features
            2. 6.2.2.2.2.2 Thermal Manager Functional Description
            3. 6.2.2.2.2.3 Thermal FSM
            4. 6.2.2.2.2.4 Thermal Alert Comparator
            5. 6.2.2.2.2.5 Thermal Shutdown Comparators
            6. 6.2.2.2.2.6 Temperature Timestamp Registers
            7. 6.2.2.2.2.7 FIFO Management
            8. 6.2.2.2.2.8 ADC Values Versus Temperature
      3. 6.2.3 Power Control Modules
        1. 6.2.3.1 Clock ICG controls
        2. 6.2.3.2 L2OCRAM Power Control
      4. 6.2.4 Device Power States
        1. 6.2.4.1 Overview of Device Power Modes
        2. 6.2.4.2 Device Power States and Transitions
    3. 6.3 Reset
      1. 6.3.1 Overview
        1. 6.3.1.1 SoC Supported Resets
      2. 6.3.2 Reset Details
        1. 6.3.2.1 PORz Reset
        2. 6.3.2.2 Warm Resets
          1. 6.3.2.2.1 Warm Reset by WARMRSTn HW Pin
          2. 6.3.2.2.2 Internal Warm Reset Sources
            1. 6.3.2.2.2.1 Thermal Alert Reset
            2. 6.3.2.2.2.2 SYS_CLK Clock Loss Reset
            3. 6.3.2.2.2.3 Voltage Monitor Error Reset
            4. 6.3.2.2.2.4 ESM Errors Reset
            5. 6.3.2.2.2.5 Debugger Reset
            6. 6.3.2.2.2.6 WDT Resets
          3. 6.3.2.2.3 SW Warm Reset
        3. 6.3.2.3 Local Module Resets
        4. 6.3.2.4 R5FSS Reset
        5. 6.3.2.5 Reset - High Heating Value (HHV)
      3. 6.3.3 Core and Cluster Reset logic
      4. 6.3.4 Reset Status
      5. 6.3.5 Reset Registers
      6. 6.3.6 Reset Power up Sequence
    4. 6.4 Clocking
      1. 6.4.1 Overview
        1. 6.4.1.1 Analog Modules
          1. 6.4.1.1.1 PLL Module
          2. 6.4.1.1.2 CORE PLL Overview
          3. 6.4.1.1.3 PER PLL Overview
          4. 6.4.1.1.4 PLL Hookup
          5. 6.4.1.1.5 HSDIVIDER Module
        2. 6.4.1.2 R5SS and SYSCLK Clock Tree
      2. 6.4.2 Clock IO
        1. 6.4.2.1 Overview
        2. 6.4.2.2 Clock IO Mapping
      3. 6.4.3 IP Clocking
        1. 6.4.3.1 IP Clocks Having GCM
        2. 6.4.3.2 IP Clocks working on SYS_CLK
        3. 6.4.3.3 Clock Selection
      4. 6.4.4 Clock Gating
      5. 6.4.5 Monitoring SYS_CLK
      6. 6.4.6 Limp Mode
      7. 6.4.7 Clocking Registers
      8. 6.4.8 Programming Guide
        1. 6.4.8.1 PLL and Root Clocks Programming Guide
          1. 6.4.8.1.1 PLL Configurations
            1. 6.4.8.1.1.1 Kick Protection Mechanism
            2. 6.4.8.1.1.2 Sequence to Configure the CORE PLL
            3. 6.4.8.1.1.3 Sequence to Configure the PER PLL
            4. 6.4.8.1.1.4 Sequence to Re-Configure the PLL
          2. 6.4.8.1.2 Root Clock Configurations
            1. 6.4.8.1.2.1 Sequence for Programming SYS and R5 Clocks
            2. 6.4.8.1.2.2 Sequence for Programming TRACE Clock
            3. 6.4.8.1.2.3 Sequence for Programming CLKOUT Clock
        2. 6.4.8.2 IP Clock Configurations
          1. 6.4.8.2.1  RTI CLOCK
          2. 6.4.8.2.2  WDT CLOCK
          3. 6.4.8.2.3  OSPI CLOCK
          4. 6.4.8.2.4  MCSPI CLOCK
          5. 6.4.8.2.5  I2C CLOCK
          6. 6.4.8.2.6  LIN_UART CLOCK
          7. 6.4.8.2.7  ICSSM UART CLOCK
          8. 6.4.8.2.8  MCAN CLOCK
          9. 6.4.8.2.9  MMCx CLOCK
          10. 6.4.8.2.10 CPTS CLOCK
          11. 6.4.8.2.11 HSM RTI CLOCK
          12. 6.4.8.2.12 HSM WDT CLOCK
          13. 6.4.8.2.13 HSM RTC CLOCK
          14. 6.4.8.2.14 HSM DMTA CLOCK
          15. 6.4.8.2.15 HSM DMTB CLOCK
          16. 6.4.8.2.16 CONTROLSS PLL CLOCK
          17. 6.4.8.2.17 RGMII5 CLK
          18. 6.4.8.2.18 RGMII50 CLK
          19. 6.4.8.2.19 RGMII250 CLK
          20. 6.4.8.2.20 XTAL MMC 32K CLOCK
          21. 6.4.8.2.21 XTAL TEMPSENSE 32K CLOCK
          22. 6.4.8.2.22 MSS_ELM CLOCK
  9. 7 Processors and Accelerators
    1. 7.1 Arm Cortex R5F Subsystem (R5FSS)
      1. 7.1.1 R5FSS Overview
        1. 7.1.1.1 R5FSS Features
        2. 7.1.1.2 R5FSS Not Supported Features
      2. 7.1.2 R5FSS Integration
        1. 7.1.2.1 R5FSS Integration
      3. 7.1.3 R5FSS Functional Description
        1. 7.1.3.1  R5FSS Block Diagram
        2. 7.1.3.2  R5FSS Cortex-R5F Core
          1. 7.1.3.2.1 L1 Caches
          2. 7.1.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 7.1.3.2.3 R5FSS Special Signals
        3. 7.1.3.3  R5FSS Interfaces
          1. 7.1.3.3.1 Initiator Interfaces
          2. 7.1.3.3.2 Target Interfaces
        4. 7.1.3.4  R5FSS Power, Clocking and Reset
          1. 7.1.3.4.1 R5FSS Power
          2. 7.1.3.4.2 R5FSS Clocking
          3. 7.1.3.4.3 R5FSS Reset
          4. 7.1.3.4.4 R5FSS Reset Sequencing
        5. 7.1.3.5  R5FSS Vectored Interrupt Manager (VIM)
        6. 7.1.3.6  R5FSS ECC Support
        7. 7.1.3.7  R5FSS Memory View
        8. 7.1.3.8  R5FSS Interrupts
        9. 7.1.3.9  R5FSS Debug and Trace
        10. 7.1.3.10 R5FSS Boot Options
        11. 7.1.3.11 R5FSS Events
          1. 7.1.3.11.1 R5FSS Core Memory ECC Events
        12. 7.1.3.12 R5FSS TCM Address Parity Error
        13. 7.1.3.13 R5FSS Lockstep Compare
          1. 7.1.3.13.1 Overview
            1. 7.1.3.13.1.1 Main Features
            2. 7.1.3.13.1.2 Block Diagram
          2. 7.1.3.13.2 Module Operation
            1. 7.1.3.13.2.1 CPU/VIM Output Compare Diagnostic
              1. 7.1.3.13.2.1.1 Active Compare lockstep Mode
              2. 7.1.3.13.2.1.2 Self-Test Mode
                1. 7.1.3.13.2.1.2.1 Compare Match Test
                2. 7.1.3.13.2.1.2.2 Compare Mismatch Test
              3. 7.1.3.13.2.1.3 Error Forcing Mode
              4. 7.1.3.13.2.1.4 Self-Test Error Forcing Mode
            2. 7.1.3.13.2.2 CPU Input Inversion Diagnostic
            3. 7.1.3.13.2.3 Checker CPU Inactivity Monitor
              1. 7.1.3.13.2.3.1 Active Compare Mode
              2. 7.1.3.13.2.3.2 Self-Test Mode
                1. 7.1.3.13.2.3.2.1 Compare Match Test
                2. 7.1.3.13.2.3.2.2 Compare Mismatch Test
              3. 7.1.3.13.2.3.3 Error Forcing Mode
              4. 7.1.3.13.2.3.4 Self-Test Error Forcing Mode
            4. 7.1.3.13.2.4 Operation During CPU Debug Mode
          3. 7.1.3.13.3 Control Registers
            1. 7.1.3.13.3.1 CCM-R5F Status Register 1 (CCMSR1)
            2. 7.1.3.13.3.2 CCM-R5F Key Register 1 (CCMKEYR1)
            3. 7.1.3.13.3.3 CCM-R5F Status Register 2 (CCMSR2)
            4. 7.1.3.13.3.4 CCM-R5F Key Register 2 (CCMKEYR2)
            5. 7.1.3.13.3.5 CCM-R5F Status Register 3 (CCMSR3)
            6. 7.1.3.13.3.6 CCM-R5F Key Register 3 (CCMKEYR3)
            7. 7.1.3.13.3.7 CCM-R5F Polarity Control Register (CCMPOLCNTRL)
        14. 7.1.3.14 R5FSS Selftest Logic
    2. 7.2 Trigonometric Math Unit (TMU)
      1. 7.2.1 TMU Introduction
        1. 7.2.1.1 TMU Supported Features
      2. 7.2.2 TMU Functional Operation
        1. 7.2.2.1 Supported Functions
        2. 7.2.2.2 TMU Module Block diagram
        3. 7.2.2.3 Operand Registers (OP1 and OP2)
        4. 7.2.2.4 Result Registers
          1. 7.2.2.4.1 Operand and Result Register Structure
        5. 7.2.2.5 Initiating TMU Operation
          1. 7.2.2.5.1 Interrupt Context Save and Restore
          2. 7.2.2.5.2 Pipelined Operation
        6. 7.2.2.6 Result Reading Methods
          1. 7.2.2.6.1 Single Operation
          2. 7.2.2.6.2 Pipelined Operation
        7. 7.2.2.7 ROM Parity Error
      3. 7.2.3 TMU Data Format
        1. 7.2.3.1 Negative Zero
        2. 7.2.3.2 De-Normalized Numbers
        3. 7.2.3.3 Underflow
        4. 7.2.3.4 Overflow
        5. 7.2.3.5 Rounding
        6. 7.2.3.6 Infinity and Not a Number (NaN)
        7. 7.2.3.7 Common Restrictions
      4. 7.2.4 TMU Operation Pseudo Code
        1. 7.2.4.1 Single Operation
        2. 7.2.4.2 Pipelined Operation
    3. 7.3 Programmable Real-Time Unit Subsystem (PRU-ICSS)
      1. 7.3.1  PRU-ICSS Overview
        1. 7.3.1.1 PRU-ICSS Key Features
        2. 7.3.1.2 Not Supported Features
        3.       388
      2. 7.3.2  PRU-ICSS Environment
        1. 7.3.2.1 PRU-ICSS Internal Pinmux
          1.        PRU-ICSS I/O Signals
        2.       392
      3. 7.3.3  PRU-ICSS Integration
      4. 7.3.4  PRU-ICSS Top Level Resources Functional Description
        1. 7.3.4.1 PRU-ICSS Reset Management
        2. 7.3.4.2 PRU-ICSS Power and Clock Management
          1. 7.3.4.2.1 PRU-ICSS CORE Clock Generation
          2. 7.3.4.2.2 PRU-ICSS Protect
          3. 7.3.4.2.3 Module Clock Configurations at PRU-ICSS Top Level
        3. 7.3.4.3 Other PRU-ICSS Module Functional Registers at Subsystem Level
        4. 7.3.4.4 PRU-ICSS Memory Maps
          1. 7.3.4.4.1 PRU-ICSS Local Memory Map
            1. 7.3.4.4.1.1 PRU-ICSS Local Instruction Memory Map
            2. 7.3.4.4.1.2 PRU-ICSS Local Data Memory Map
          2. 7.3.4.4.2 PRU-ICSS Global Memory Map
        5.       406
      5. 7.3.5  PRU-ICSS PRU Cores
        1. 7.3.5.1 PRU Cores Overview
        2. 7.3.5.2 PRU Cores Functional Description
          1. 7.3.5.2.1 PRU Constant Table
          2. 7.3.5.2.2 PRU Module Interface
            1. 7.3.5.2.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input
            2. 7.3.5.2.2.2 Event Interface Mapping (R31): PRU System Events
            3. 7.3.5.2.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module
              1. 7.3.5.2.2.3.1 PRU EGPIs Direct Input
              2. 7.3.5.2.2.3.2 PRU EGPIs 16-Bit Parallel Capture
              3. 7.3.5.2.2.3.3 PRU EGPIs 28-Bit Shift In
                1. 7.3.5.2.2.3.3.1 PRU EGPI Programming Model
              4. 7.3.5.2.2.3.4 General-Purpose Outputs (R30): Enhanced PRU GP Module
                1. 7.3.5.2.2.3.4.1 PRU EGPOs Direct Output
                2. 7.3.5.2.2.3.4.2 PRU EGPO Shift Out
                  1. 3.5.2.2.3.4.2.1 PRU EGPO Programming Model
              5. 7.3.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering
                1. 7.3.5.2.2.3.5.1 Sigma Delta Block Diagram and Signals
                2. 7.3.5.2.2.3.5.2 PRU R30 / R31 Interface
                3. 7.3.5.2.2.3.5.3 Sigma Delta Description
                4. 7.3.5.2.2.3.5.4 Sigma Delta Basic Programming Example
              6. 7.3.5.2.2.3.6 Three Channel Peripheral Interface
                1. 7.3.5.2.2.3.6.1 Peripheral Interface Block Diagram and Signal Configuration
                2. 7.3.5.2.2.3.6.2 PRU R30 and R31 Interface
                3. 7.3.5.2.2.3.6.3 Clock Generation
                  1. 3.5.2.2.3.6.3.1 Configuration
                  2. 3.5.2.2.3.6.3.2 Clock Output Start Conditions
                    1. 5.2.2.3.6.3.2.1 TX Mode (RX_EN = 0)
                    2. 5.2.2.3.6.3.2.2 RX Mode (RX_EN = 1)
                  3. 3.5.2.2.3.6.3.3 Stop Conditions
                4. 7.3.5.2.2.3.6.4 Three Peripheral Mode Basic Programming Model
                  1. 3.5.2.2.3.6.4.1 Clock Generation
                  2. 3.5.2.2.3.6.4.2 TX - Single Shot
                  3. 3.5.2.2.3.6.4.3 TX - Continuous FIFO Loading
                  4. 3.5.2.2.3.6.4.4 RX - Auto Arm or Non-Auto Arm
        3. 7.3.5.3 PRU-ICSS RAM Index Allocation
        4.       443
      6. 7.3.6  PRU-ICSS Broadside Accelerators
        1. 7.3.6.1 PRU-ICSS Broadside Accelerators Overview
        2. 7.3.6.2 PRU-ICSS Data Processing Accelerators Functional
          1. 7.3.6.2.1 PRU Multiplier with Accumulation (MPY/MAC)
            1. 7.3.6.2.1.1 PRU MAC Operations
              1. 7.3.6.2.1.1.1 PRU versus MAC Interface
              2. 7.3.6.2.1.1.2 Multiply only mode(default state), MAC_MODE = 0
                1. 7.3.6.2.1.1.2.1 Programming PRU MAC in "Multiply-ONLY" mode
              3. 7.3.6.2.1.1.3 Multiply and Accumulate Mode, MAC_MODE = 1
                1. 7.3.6.2.1.1.3.1 Programming PRU MAC in Multiply and Accumulate Mode
          2. 7.3.6.2.2 PRU CRC16/32 Module
            1. 7.3.6.2.2.1 PRU and CRC16/32 Interface
            2. 7.3.6.2.2.2 CRC Programming Model
            3. 7.3.6.2.2.3 PRU and CRC16/32 Interface (R9:R2)
          3. 7.3.6.2.3 PRU-ICSS Scratch Pad Memory
            1. 7.3.6.2.3.1 PRU0/1 Scratch Pad Overview
            2. 7.3.6.2.3.2 PRU0 /1 Scratch Pad Operations
              1. 7.3.6.2.3.2.1 Optional XIN/XOUT Shift
              2. 7.3.6.2.3.2.2 Scratch Pad Operations Examples
        3. 7.3.6.3 PRU-ICSS Data Movement Accelerators Functional
          1. 7.3.6.3.1 PRU-ICSS XFR2VBUS Hardware Accelerator
            1. 7.3.6.3.1.1 Blocking Conditions
            2. 7.3.6.3.1.2 Read Operation with Auto Disabled
            3. 7.3.6.3.1.3 Read Operation with Auto Enabled
            4. 7.3.6.3.1.4 PRU to XFR2VBUS Interface
            5. 7.3.6.3.1.5 XFR2VBUS Programming Model
        4.       470
      7. 7.3.7  PRU-ICSS Local INTC
        1. 7.3.7.1 PRU-ICSS Interrupt Controller Functional Description
          1. 7.3.7.1.1 PRU-ICSS Interrupt Controller System Events Flow
            1. 7.3.7.1.1.1 PRU-ICSS Interrupt Processing
              1. 7.3.7.1.1.1.1 PRU-ICSS Interrupt Enabling
            2. 7.3.7.1.1.2 PRU-ICSS Interrupt Status Checking
            3. 7.3.7.1.1.3 PRU-ICSS Interrupt Channel Mapping
              1. 7.3.7.1.1.3.1 PRU-ICSS Host Interrupt Mapping
              2. 7.3.7.1.1.3.2 PRU-ICSS Interrupt Prioritization
            4. 7.3.7.1.1.4 PRU-ICSS Interrupt Nesting
            5. 7.3.7.1.1.5 PRU-ICSS Interrupt Status Clearing
          2. 7.3.7.1.2 PRU-ICSS Interrupt Disabling
        2. 7.3.7.2 PRU-ICSS Interrupt Controller Basic Programming Model
        3. 7.3.7.3 PRU-ICSS Interrupt Requests Mapping
        4.       485
      8. 7.3.8  PRU-ICSS UART Module
        1. 7.3.8.1 PRU-ICSS UART Overview
        2. 7.3.8.2 PRU-ICSS UART Environment
          1. 7.3.8.2.1 PRU-ICSS UART Pin Multiplexing
          2. 7.3.8.2.2 PRU-ICSS UART Signal Descriptions
          3. 7.3.8.2.3 PRU-ICSS UART Protocol Description and Data Format
            1. 7.3.8.2.3.1 PRU-ICSS UART Transmission Protocol
            2. 7.3.8.2.3.2 PRU-ICSS UART Reception Protocol
            3. 7.3.8.2.3.3 PRU-ICSS UART Data Format
              1. 7.3.8.2.3.3.1 Frame Formatting
          4. 7.3.8.2.4 PRU-ICSS UART Clock Generation and Control
        3. 7.3.8.3 PRU-ICSS UART Functional Description
          1. 7.3.8.3.1 PRU-ICSS UART Functional Block Diagram
          2. 7.3.8.3.2 PRU-ICSS UART Reset Considerations
            1. 7.3.8.3.2.1 PRU-ICSS UART Software Reset Considerations
            2. 7.3.8.3.2.2 PRU-ICSS UART Hardware Reset Considerations
          3. 7.3.8.3.3 PRU-ICSS UART Power Management
          4. 7.3.8.3.4 PRU-ICSS UART Interrupt Support
            1. 7.3.8.3.4.1 PRU-ICSS UART Interrupt Events and Requests
            2. 7.3.8.3.4.2 PRU-ICSS UART Interrupt Multiplexing
          5. 7.3.8.3.5 PRU-ICSS UART DMA Event Support
          6. 7.3.8.3.6 PRU-ICSS UART Operations
            1. 7.3.8.3.6.1 PRU-ICSS UART FIFO Modes
              1. 7.3.8.3.6.1.1 PRU-ICSS UART FIFO Interrupt Mode
              2. 7.3.8.3.6.1.2 PRU-ICSS UART FIFO Poll Mode
            2. 7.3.8.3.6.2 PRU-ICSS UART Autoflow Control
              1. 7.3.8.3.6.2.1 PRU-ICSS UART Signal UART0_RTS Behavior
              2. 7.3.8.3.6.2.2 PRU-ICSS UART Signal UART0_CTS Behavior
            3. 7.3.8.3.6.3 PRU-ICSS UART Loopback Control
          7. 7.3.8.3.7 PRU-ICSS UART Emulation Considerations
          8. 7.3.8.3.8 PRU-ICSS UART Exception Processing
            1. 7.3.8.3.8.1 PRU-ICSS UART Divisor Latch Not Programmed
            2. 7.3.8.3.8.2 Changing Operating Mode During Busy Serial Communication of PRU-ICSS UART
        4.       519
      9. 7.3.9  PRU-ICSS ECAP Module
        1. 7.3.9.1 PRU-ICSS eCAP Overview
          1. 7.3.9.1.1 Purpose of the PRU-ICSS eCAP Peripheral
          2. 7.3.9.1.2 PRU-ICSS eCAP Features
        2. 7.3.9.2 PRU-ICSS ECAP Functional Description
          1. 7.3.9.2.1 PRU-ICSS Capture and APWM Operating Mode
          2. 7.3.9.2.2 PRU-ICSS eCAP Capture Mode Description
            1. 7.3.9.2.2.1 PRU-ICSS eCAP Event Prescaler
            2. 7.3.9.2.2.2 PRU-ICSS eCAP Edge Polarity Select and Qualifier
            3. 7.3.9.2.2.3 eCAP Continuous/One-Shot Control
            4. 7.3.9.2.2.4 PRU-ICSS eCAP 32-bit Counter and Phase Control
            5. 7.3.9.2.2.5 PRU-ICSS Enhanced Capture CAP1-CAP4 Registers
            6. 7.3.9.2.2.6 PRU-ICSS eCAP Interrupt Control
            7. 7.3.9.2.2.7 PRU-ICSS eCAP Shadow Load and Lockout Control
            8. 7.3.9.2.2.8 CEVT Flag Registers
          3. 7.3.9.2.3 PRU-ICSS eCAP Module APWM Mode Operation
          4. 7.3.9.2.4 Use Cases
            1. 7.3.9.2.4.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
              1. 7.3.9.2.4.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
            2. 7.3.9.2.4.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
              1. 7.3.9.2.4.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
            3. 7.3.9.2.4.3 Time Difference (Delta) Operation Rising Edge Trigger Example
              1. 7.3.9.2.4.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
            4. 7.3.9.2.4.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
              1. 7.3.9.2.4.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
            5. 7.3.9.2.4.5 Application of the APWM Mode
              1. 7.3.9.2.4.5.1 Simple PWM Generation (Independent Channel/s) Example
                1. 7.3.9.2.4.5.1.1 Code Snippet for APWM Mode
              2. 7.3.9.2.4.5.2 Multichannel PWM Generation with Synchronization Example
                1. 7.3.9.2.4.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
              3. 7.3.9.2.4.5.3 Multichannel PWM Generation with Phase Control Example
                1. 7.3.9.2.4.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        3.       552
      10. 7.3.10 PRU-ICSS MII_RT Module
        1. 7.3.10.1 PRU-ICSS MII_RT Introduction
          1. 7.3.10.1.1 PRU-ICSS MII_RT Features
          2. 7.3.10.1.2 Unsupported Features
          3. 7.3.10.1.3 PRU-ICSS MII_RT Block Diagram
        2. 7.3.10.2 MII_RT Functional Description
          1. 7.3.10.2.1 MII_RT Data Path Configuration
            1. 7.3.10.2.1.1 Auto-forward with Optional PRU Snoop
            2. 7.3.10.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications
            3. 7.3.10.2.1.3 32-byte Double Buffer or Ping-Pong Processing
          2. 7.3.10.2.2 MII_RT Definition and Terms
            1. 7.3.10.2.2.1 MII_RT Data Frame Structure
            2. 7.3.10.2.2.2 PRU R30 and R31
            3. 7.3.10.2.2.3 RX and TX L1 FIFO Data Movement
            4. 7.3.10.2.2.4 Receive CRC Computation
            5. 7.3.10.2.2.5 Transmit CRC Computation
            6. 7.3.10.2.2.6 Transmit CRC Computation for fragmented frames
          3. 7.3.10.2.3 RX MII Interface
            1. 7.3.10.2.3.1 RX MII Receive Data Latch
            2. 7.3.10.2.3.2 RX MII Start of Frame Detection
            3. 7.3.10.2.3.3 CRC Error Detection
            4. 7.3.10.2.3.4 RX Error Detection and Action
            5. 7.3.10.2.3.5 RX Data Path Options to PRU
            6. 7.3.10.2.3.6 RX MII Port → RX L1 FIFO → PRU
            7. 7.3.10.2.3.7 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
              1. 7.3.10.2.3.7.1 RX L2 Status in mode 0, none IET mode (when ICSS_M_CFG[2] RX_L2_G_EN= 0h)
              2. 7.3.10.2.3.7.2 RX L2 XFR Identification
              3. 7.3.10.2.3.7.3 RX L2 XFR Status
              4. 7.3.10.2.3.7.4 Broadside Stitch FIFO
          4. 7.3.10.2.4 PRU-ICSS TX MII Interface
            1. 7.3.10.2.4.1 TX Data Path Options to TX L1 FIFO
              1. 7.3.10.2.4.1.1 PRU → TX L1 FIFO → TX MII Port
                1. 7.3.10.2.4.1.1.1 TX L2 FIFO Features
                2. 7.3.10.2.4.1.1.2 TX Insertion
                3. 7.3.10.2.4.1.1.3 TX Preemption
                  1. 3.10.2.4.1.1.3.1 TX Preemption Programming Model
              2. 7.3.10.2.4.1.2 RX L1 FIFO → TX L1 FIFO (Direct Connection) → TX MII Port
          5. 7.3.10.2.5 PRU R31 Command Interface
          6. 7.3.10.2.6 Other Configuration Options
            1. 7.3.10.2.6.1 Nibble and Byte Order
            2. 7.3.10.2.6.2 MII_RT Preamble Source
            3. 7.3.10.2.6.3 PRU and MII Port Multiplexer
              1. 7.3.10.2.6.3.1 Receive Multiplexer
              2. 7.3.10.2.6.3.2 Transmit Multiplexer
            4. 7.3.10.2.6.4 RX L2 Scratch Pad
        3.       598
      11. 7.3.11 PRU-ICSS MII MDIO Module
        1. 7.3.11.1 PRU-ICSS MII MDIO Overview
        2. 7.3.11.2 PRU-ICSS MII MDIO Functional Description
          1. 7.3.11.2.1 MDIO Clause 22 Frame Formats
            1. 7.3.11.2.1.1 PRU-ICSS MDIO Control and Interface Signals
          2. 7.3.11.2.2 MDIO Clause 45 Frame Formats
          3. 7.3.11.2.3 PRU-ICSS MII MDIO Interractions
          4. 7.3.11.2.4 PRU-ICSS MII MDIO Interrupts
            1. 7.3.11.2.4.1 Normal Mode ([30]STATECHANGEMODE = 0h)
            2. 7.3.11.2.4.2 State Change Mode ([30]STATECHANGEMODE = 1h)
          5. 7.3.11.2.5 Manual Mode
        3. 7.3.11.3 PRU-ICSS MII MDIO Receive/Transmit Frame Host Software Interface
        4.       611
      12. 7.3.12 PRU-ICSS IEP
        1. 7.3.12.1 PRU-ICSS IEP Overview
        2. 7.3.12.2 PRU-ICSS IEP Functional Description
          1. 7.3.12.2.1 PRU-ICSS IEP Clock Generation
          2. 7.3.12.2.2 PRU-ICSS IEP Timer
            1. 7.3.12.2.2.1 PRU-ICSS IEP Timer Features
          3. 7.3.12.2.3 32-Bit Shadow Mode
          4. 7.3.12.2.4 PRU-ICSS IEP Timer Basic Programming Sequence
          5. 7.3.12.2.5 Industrial Ethernet Mapping
          6. 7.3.12.2.6 PRU-ICSS IEP Sync0/Sync1 Module
            1. 7.3.12.2.6.1 PRU-ICSS IEP Sync0/Sync1 Features
            2. 7.3.12.2.6.2 PRU-ICSS IEP Sync0/Sync1 Generation Modes
          7. 7.3.12.2.7 PRU-ICSS IEP WatchDog
          8. 7.3.12.2.8 PRU-ICSS IEP DIGIO
            1. 7.3.12.2.8.1 PRU-ICSS IEP DIGIO Features
            2. 7.3.12.2.8.2 PRU-ICSS IEP DIGIO Block Diagrams
            3. 7.3.12.2.8.3 PRU-ICSS IEP Basic Programming Model
        3.       629
    4. 7.4 Hardware Security Module (HSM)
      1. 7.4.1 Security Features
      2. 7.4.2 Security Features not Supported
      3. 7.4.3 Security Device Types
      4. 7.4.4 How to Request Access for HSM Addendum
    5. 7.5 Real-time Control Subsystem (CONTROLSS)
      1. 7.5.1  Real-time Control Subsystem (CONTROLSS) Overview
      2. 7.5.2  Analog-to-Digital Converter (ADC)
        1. 7.5.2.1  Introduction (ADC)
          1. 7.5.2.1.1 Features
        2. 7.5.2.2  ADC Integration
        3. 7.5.2.3  ADC Configurability
          1. 7.5.2.3.1 Clock Configuration
          2. 7.5.2.3.2 Resolution
          3. 7.5.2.3.3 Voltage Reference
            1. 7.5.2.3.3.1 Internal ADC Voltage Reference Buffer Control
          4. 7.5.2.3.4 ADC Modes of Operation
          5. 7.5.2.3.5 ADC Usage and Configuration Note
          6. 7.5.2.3.6 Interpreting Conversion Results
          7. 7.5.2.3.7 ADC-CMPSS Signal Connections
        4. 7.5.2.4  SOC Principle of Operation
        5. 7.5.2.5  SOC Configuration
        6. 7.5.2.6  Trigger Operation
          1. 7.5.2.6.1 Global Software Trigger
          2. 7.5.2.6.2 Trigger Repeaters
            1. 7.5.2.6.2.1 Oversampling Mode
            2. 7.5.2.6.2.2 Undersampling Mode
            3. 7.5.2.6.2.3 Trigger Phase Delay
            4. 7.5.2.6.2.4 Re-trigger Spread
            5. 7.5.2.6.2.5 Trigger Repeater Configuration
              1. 7.5.2.6.2.5.1 Register Shadow Updates
            6. 7.5.2.6.2.6 Re-Trigger Logic
            7. 7.5.2.6.2.7 Multi-Path Triggering Behavior
        7. 7.5.2.7  ADC Acquisition (Sample and Hold) Window
        8. 7.5.2.8  ADC Input Models
        9. 7.5.2.9  Channel Selection
          1. 7.5.2.9.1 External Channel Selection
          2. 7.5.2.9.2 External Channel Selection Timing
        10. 7.5.2.10 SOC Configuration Examples
          1. 7.5.2.10.1 Single Conversion from ePWM Trigger
          2. 7.5.2.10.2 Oversampled Conversion from ePWM Trigger
          3. 7.5.2.10.3 Software Triggering of SOCs
        11. 7.5.2.11 ADC Conversion Priority
        12. 7.5.2.12 Burst Mode
          1. 7.5.2.12.1 Burst Mode Example
          2. 7.5.2.12.2 Burst Mode Priority Example
        13. 7.5.2.13 EOC and Interrupt Operation
          1. 7.5.2.13.1 Interrupt Overflow
          2. 7.5.2.13.2 Continue to Interrupt Mode
          3. 7.5.2.13.3 Early Interrupt Configuration Mode
        14. 7.5.2.14 Post-Processing Blocks
          1. 7.5.2.14.1 PPB Offset Correction
          2. 7.5.2.14.2 PPB Error Calculation
          3. 7.5.2.14.3 PPB Limit Detection and Zero-Crossing Detection
          4. 7.5.2.14.4 PPB Sample Delay Capture
          5. 7.5.2.14.5 PPB Oversampling
            1. 7.5.2.14.5.1 Accumulation, Minimum, Maximum, and Average Functions
            2. 7.5.2.14.5.2 Outlier Rejection
        15. 7.5.2.15 Result Safety Checker
          1. 7.5.2.15.1 Result Safety Checker Operation
          2. 7.5.2.15.2 Result Safety Checker Interrupts and Events
        16. 7.5.2.16 Opens/Shorts Detection Circuit (OSDETECT)
          1. 7.5.2.16.1 Implementation
          2. 7.5.2.16.2 Detecting an Open Input Pin
          3. 7.5.2.16.3 Detecting a Shorted Input Pin
          4. 7.5.2.16.4 ADC OSD Programming Guide
        17. 7.5.2.17 Power-Up Sequence
        18. 7.5.2.18 ADC Calibration
          1. 7.5.2.18.1 ADC Zero Offset Calibration
        19. 7.5.2.19 ADC Timings
          1. 7.5.2.19.1 ADC Timing Diagrams
        20. 7.5.2.20 Additional Information
          1. 7.5.2.20.1 Ensuring Synchronous Operation
            1. 7.5.2.20.1.1 Basic Synchronous Operation
            2. 7.5.2.20.1.2 Synchronous Operation with Multiple Trigger Sources
            3. 7.5.2.20.1.3 Synchronous Operation with Uneven SOC Numbers
            4. 7.5.2.20.1.4 Non-overlapping Conversions
          2. 7.5.2.20.2 Choosing an Acquisition Window Duration
          3. 7.5.2.20.3 Achieving Simultaneous Sampling
          4. 7.5.2.20.4 Result Register Mapping
      3. 7.5.3  Resolver to Digital Converter (RDC)
        1. 7.5.3.1 Overview
          1. 7.5.3.1.1 Principle of Operation
          2. 7.5.3.1.2 Supported Features
          3. 7.5.3.1.3 Safety Features
          4. 7.5.3.1.4 Performance Specification
          5. 7.5.3.1.5 Fault Detection Support
        2. 7.5.3.2 Integration
          1. 7.5.3.2.1 Resolver to Digital Convertor Integration
          2. 7.5.3.2.2 Functional Description
            1. 7.5.3.2.2.1 Resolver to Digital Converter(RDC) Sub System
              1. 7.5.3.2.2.1.1  Sequencer and RDC Modes of Operation
                1. 7.5.3.2.2.1.1.1 Mode 0
                2. 7.5.3.2.2.1.1.2 Mode 1
                3. 7.5.3.2.2.1.1.3 Mode 2
                4. 7.5.3.2.2.1.1.4 Mode 3
                5. 7.5.3.2.2.1.1.5 Mode 4
                6. 7.5.3.2.2.1.1.6 Mode 5
              2. 7.5.3.2.2.1.2  Excitation Signal and PWM
              3. 7.5.3.2.2.1.3  Offset Correction
              4. 7.5.3.2.2.1.4  Auto Sample Time Select
                1. 7.5.3.2.2.1.4.1 Ideal Sample Mode 0
                2. 7.5.3.2.2.1.4.2 Ideal Sample Mode 1
                3. 7.5.3.2.2.1.4.3 Ideal Sample Mode 2
                4. 7.5.3.2.2.1.4.4 Ideal Sample Mode 3
              5. 7.5.3.2.2.1.5  Automatic Gain and Phase Correction
              6. 7.5.3.2.2.1.6  Glitch Filter and Decimation
              7. 7.5.3.2.2.1.7  Arctan
              8. 7.5.3.2.2.1.8  Track2
              9. 7.5.3.2.2.1.9  ADC part of Resolver to Digital Converter
              10. 7.5.3.2.2.1.10 Interrupts
        3. 7.5.3.3 Programmer's Guide
          1. 7.5.3.3.1 RDC Diagnostics
            1. 7.5.3.3.1.1 Monitor Sin or Cos DC offset drift (DOS)
            2. 7.5.3.3.1.2 Monitor Sin or Cos Gain drift (DOS)
            3. 7.5.3.3.1.3 Monitor Sin or Cos Phase drift (DOS)
            4. 7.5.3.3.1.4 Monitor degradation/loss of excitation frequency (DOS)
            5. 7.5.3.3.1.5 Monitor Rotational Signal Integrity (DOS)
            6. 7.5.3.3.1.6 Monitor Signal Integrity by checking Sin2 + Cos2 = Constant (DOS)
            7. 7.5.3.3.1.7 Monitor Very high amplitude or Saturation of Sine and Cosine Signals (DOS)
            8. 7.5.3.3.1.8 Monitor weak Sine and Cosine Signals (LOS)
      4. 7.5.4  Comparator Subsystem (CMPSS)
        1. 7.5.4.1 Introduction
          1. 7.5.4.1.1 Features
          2. 7.5.4.1.2 Comparator
          3. 7.5.4.1.3 Block Diagram
        2. 7.5.4.2 ADC-CMPSS Signal Connections
        3. 7.5.4.3 Reference DAC
        4. 7.5.4.4 Ramp Generator
          1. 7.5.4.4.1 Ramp Generator Overview
          2. 7.5.4.4.2 Ramp Generator Behavior
          3. 7.5.4.4.3 Ramp Generator Behavior at Corner Cases
        5. 7.5.4.5 Digital Filter
          1. 7.5.4.5.1 Filter Initialization Sequence
        6. 7.5.4.6 Using the CMPSS
          1. 7.5.4.6.1 LATCHCLR, EPWMSYNCPER and EPWMBLANK Signals
          2. 7.5.4.6.2 Synchronizer, Digital Filter, and Latch Delays
          3. 7.5.4.6.3 Calibrating the CMPSS Trip Levels
            1. 7.5.4.6.3.1 CMPSS Hysteresis
        7. 7.5.4.7 Enabling and Disabling the CMPSS Clock
        8. 7.5.4.8 CMPSS Programming Guide
      5. 7.5.5  Buffered Digital-to-Analog Converter (DAC)
        1. 7.5.5.1 Introduction
          1. 7.5.5.1.1 DAC Features
          2. 7.5.5.1.2 Block Diagram
        2. 7.5.5.2 Using the DAC
          1. 7.5.5.2.1 Initialization Sequence
          2. 7.5.5.2.2 DAC Offset Adjustment
          3. 7.5.5.2.3 EPWMSYNCPER Signal
        3. 7.5.5.3 Lock Registers
        4. 7.5.5.4 DAC Programming Guide
      6. 7.5.6  Enhanced Pulse Width Modulator (ePWM)
        1. 7.5.6.1  Introduction
          1. 7.5.6.1.1 EPWM Related Collateral
          2. 7.5.6.1.2 Submodule Overview
        2. 7.5.6.2  EPWM Integration
        3. 7.5.6.3  ePWM Modules Overview
        4. 7.5.6.4  Time-Base (TB) Submodule
          1. 7.5.6.4.1 Purpose of the Time-Base Submodule
          2. 7.5.6.4.2 Controlling and Monitoring the Time-Base Submodule
          3. 7.5.6.4.3 Calculating PWM Period and Frequency
            1. 7.5.6.4.3.1 Time-Base Period Shadow Register
            2. 7.5.6.4.3.2 Time-Base Clock Synchronization
            3. 7.5.6.4.3.3 Time-Base Counter Synchronization
            4. 7.5.6.4.3.4 ePWM SYNC Selection
          4. 7.5.6.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
          5. 7.5.6.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
          6. 7.5.6.4.6 Time-Base Counter Modes and Timing Waveforms
          7. 7.5.6.4.7 Edge Detection Within a Programmable TBCTR Range
          8. 7.5.6.4.8 Global Load
            1. 7.5.6.4.8.1 Global Load Pulse Pre-Scalar
            2. 7.5.6.4.8.2 One-Shot Load Mode
            3. 7.5.6.4.8.3 One-Shot Sync Mode
        5. 7.5.6.5  Counter-Compare (CC) Submodule
          1. 7.5.6.5.1 Purpose of the Counter-Compare Submodule
          2. 7.5.6.5.2 Controlling and Monitoring the Counter-Compare Submodule
          3. 7.5.6.5.3 Operational Highlights for the Counter-Compare Submodule
          4. 7.5.6.5.4 Count Mode Timing Waveforms
        6. 7.5.6.6  Action-Qualifier (AQ) Submodule
          1. 7.5.6.6.1 Purpose of the Action-Qualifier Submodule
          2. 7.5.6.6.2 Action-Qualifier Submodule Control and Status Register Definitions
          3. 7.5.6.6.3 Action-Qualifier Event Priority
          4. 7.5.6.6.4 AQCTLA and AQCTLB Shadow Mode Operations
          5. 7.5.6.6.5 Configuration Requirements for Common Waveforms
        7. 7.5.6.7  Dead-Band Generator (DB) Submodule
          1. 7.5.6.7.1 Purpose of the Dead-Band Submodule
          2. 7.5.6.7.2 Dead-band Submodule Additional Operating Modes
          3. 7.5.6.7.3 Simultaneous Writes to DBRED and DBFED Registers Between ePWM Modules (Type 5 EPWM)
          4. 7.5.6.7.4 Operational Highlights for the Dead-Band Submodule
        8. 7.5.6.8  Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
          1. 7.5.6.8.1 Minimum Dead-Band (MINDB)
          2. 7.5.6.8.2 Illegal Combo Logic (ICL)
        9. 7.5.6.9  PWM Chopper (PC) Submodule
          1. 7.5.6.9.1 Purpose of the PWM Chopper Submodule
          2. 7.5.6.9.2 Operational Highlights for the PWM Chopper Submodule
          3. 7.5.6.9.3 Waveforms
            1. 7.5.6.9.3.1 One-Shot Pulse
            2. 7.5.6.9.3.2 Duty Cycle Control
        10. 7.5.6.10 Trip-Zone (TZ) Submodule
          1. 7.5.6.10.1 Purpose of the Trip-Zone Submodule
          2. 7.5.6.10.2 Operational Highlights for the Trip-Zone Submodule
            1. 7.5.6.10.2.1 Trip-Zone Configurations
          3. 7.5.6.10.3 Generating Trip Event Interrupts
        11. 7.5.6.11 Diode Emulation (DE) Submodule
          1. 7.5.6.11.1 DEACTIVE Mode
          2. 7.5.6.11.2 Exiting DE Mode
          3. 7.5.6.11.3 Re-Entering DE Mode
          4. 7.5.6.11.4 DE Monitor
        12. 7.5.6.12 Event-Trigger (ET) Submodule
          1. 7.5.6.12.1 Operational Overview of the ePWM Event-Trigger Submodule
        13. 7.5.6.13 Digital Compare (DC) Submodule
          1. 7.5.6.13.1 Purpose of the Digital Compare Submodule
          2. 7.5.6.13.2 Enhanced Trip Action Using CMPSS
          3. 7.5.6.13.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
          4. 7.5.6.13.4 Operation Highlights of the Digital Compare Submodule
            1. 7.5.6.13.4.1 Digital Compare Events
            2. 7.5.6.13.4.2 Valley Switching
            3. 7.5.6.13.4.3 Event Filtering
            4. 7.5.6.13.4.4 Event Detection
              1. 7.5.6.13.4.4.1 Input Signal Detection
              2. 7.5.6.13.4.4.2 MIN and MAX Detection Circuit
        14. 7.5.6.14 XCMP Submodule
          1. 7.5.6.14.1 XCMP Complex Waveform Generator Mode
          2. 7.5.6.14.2 MIN-MAX Event Logic
          3. 7.5.6.14.3 XCMP Shadow Buffers
          4. 7.5.6.14.4 XCMP Allocation to CMPA and CMPB
          5. 7.5.6.14.5 XCMP Operation
        15. 7.5.6.15 High-Resolution Pulse Width Modulator (HRPWM)
          1. 7.5.6.15.1 Operational Description of HRPWM
            1. 7.5.6.15.1.1 Controlling the HRPWM Capabilities
            2. 7.5.6.15.1.2 HRPWM Source Clock
            3. 7.5.6.15.1.3 Configuring the HRPWM
            4. 7.5.6.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
            5. 7.5.6.15.1.5 Principle of Operation
              1. 7.5.6.15.1.5.1 Edge Positioning
              2. 7.5.6.15.1.5.2 Scaling Considerations
              3. 7.5.6.15.1.5.3 Duty Cycle Range Limitation
              4. 7.5.6.15.1.5.4 High-Resolution Period
                1. 7.5.6.15.1.5.4.1 High-Resolution Period Configuration
            6. 7.5.6.15.1.6 Deadband High-Resolution Operation
            7. 7.5.6.15.1.7 Scale Factor Optimizing Software (SFO)
            8. 7.5.6.15.1.8 HRPWM Examples Using Optimized Assembly Code
              1. 7.5.6.15.1.8.1 #Defines for HRPWM Header Files
              2. 7.5.6.15.1.8.2 Implementing a Simple Buck Converter
                1. 7.5.6.15.1.8.2.1 HRPWM Buck Converter Initialization Code
                2. 7.5.6.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
              3. 7.5.6.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
                1. 7.5.6.15.1.8.3.1 PWM DAC Function Initialization Code
                2. 7.5.6.15.1.8.3.2 PWM DAC Function Run-Time Code
        16. 7.5.6.16 ePWM Crossbar (XBAR)
        17. 7.5.6.17 Applications to Power Topologies
          1. 7.5.6.17.1  Overview of Multiple Modules
          2. 7.5.6.17.2  Key Configuration Capabilities
          3. 7.5.6.17.3  Controlling Multiple Buck Converters With Independent Frequencies
          4. 7.5.6.17.4  Controlling Multiple Buck Converters With Same Frequencies
          5. 7.5.6.17.5  Controlling Multiple Half H-Bridge (HHB) Converters
          6. 7.5.6.17.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
          7. 7.5.6.17.7  Practical Applications Using Phase Control Between PWM Modules
          8. 7.5.6.17.8  Controlling a 3-Phase Interleaved DC/DC Converter
          9. 7.5.6.17.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
          10. 7.5.6.17.10 Controlling a Peak Current Mode Controlled Buck Module
          11. 7.5.6.17.11 Controlling H-Bridge LLC Resonant Converter
        18. 7.5.6.18 EPWM Programming Guide
      7. 7.5.7  Enhanced Capture (eCAP)
        1. 7.5.7.1  Introduction
          1. 7.5.7.1.1 Features
        2. 7.5.7.2  eCAP Integration
          1. 7.5.7.2.1 eCAP Input Selection
        3. 7.5.7.3  Description
        4. 7.5.7.4  Capture Mode Description
          1. 7.5.7.4.1  Event Prescaler
          2. 7.5.7.4.2  Glitch Filter
          3. 7.5.7.4.3  Input Capture Signal Selection
          4. 7.5.7.4.4  Modulo 4 Counter
          5. 7.5.7.4.5  Edge Polarity Select and Qualifier
          6. 7.5.7.4.6  Continuous/One-Shot Control
          7. 7.5.7.4.7  32-Bit Counter and Phase Control
          8. 7.5.7.4.8  CAP1-CAP4 Registers
          9. 7.5.7.4.9  eCAP Synchronization
            1. 7.5.7.4.9.1 Example 1 - Using SWSYNC with ECAP Module
          10. 7.5.7.4.10 DMA Interrupt
          11. 7.5.7.4.11 ADC SOC Event
          12. 7.5.7.4.12 APWM Mode Operation
          13. 7.5.7.4.13 Signal Monitoring Unit
            1. 7.5.7.4.13.1 Pulse Width and Period Monitoring
            2. 7.5.7.4.13.2 Edge Monitoring
        5. 7.5.7.5  APWM Mode Operation
        6. 7.5.7.6  eCAP Synchronization and Events
          1. 7.5.7.6.1 eCAP Synchronization
            1. 7.5.7.6.1.1 Example 1 - Using SWSYNC with ECAP Module
          2. 7.5.7.6.2 Interrupt Control
          3. 7.5.7.6.3 DMA Interrupt
          4. 7.5.7.6.4 ADC SOC Event
          5. 7.5.7.6.5 Shadow Load and Lockout Control
        7. 7.5.7.7  Signal Monitoring Unit
          1. 7.5.7.7.1 Pulse Width and Period Monitoring
          2. 7.5.7.7.2 Edge Monitoring
          3. 7.5.7.7.3 Error Events
          4. 7.5.7.7.4 Disabling the Signal Monitoring Unit
          5. 7.5.7.7.5 Shadow Control
          6. 7.5.7.7.6 Trip Signal
        8. 7.5.7.8  Application of the eCAP Module
          1. 7.5.7.8.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
          2. 7.5.7.8.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
          3. 7.5.7.8.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
          4. 7.5.7.8.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
        9. 7.5.7.9  Application of the APWM Mode
          1. 7.5.7.9.1 Example 1 - Simple PWM Generation (Independent Channels)
        10. 7.5.7.10 eCAP Programming Guide
      8. 7.5.8  Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.5.8.1  Introduction
        2. 7.5.8.2  Configuring Device Pins
        3. 7.5.8.3  EQEP Integration
        4. 7.5.8.4  Description
          1. 7.5.8.4.1 EQEP Inputs
          2. 7.5.8.4.2 Functional Description
          3. 7.5.8.4.3 eQEP Memory Map
        5. 7.5.8.5  Quadrature Decoder Unit (QDU)
          1. 7.5.8.5.1 Position Counter Input Modes
            1. 7.5.8.5.1.1 Quadrature Count Mode
            2. 7.5.8.5.1.2 Direction-Count Mode
            3. 7.5.8.5.1.3 Up-Count Mode
            4. 7.5.8.5.1.4 Down-Count Mode
          2. 7.5.8.5.2 eQEP Input Polarity Selection
          3. 7.5.8.5.3 Position-Compare Sync Output
        6. 7.5.8.6  Position Counter and Control Unit (PCCU)
          1. 7.5.8.6.1 Position Counter Operating Modes
            1. 7.5.8.6.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
            2. 7.5.8.6.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
            3. 7.5.8.6.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
            4. 7.5.8.6.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
          2. 7.5.8.6.2 Position Counter Latch
            1. 7.5.8.6.2.1 Index Event Latch
            2. 7.5.8.6.2.2 Strobe Event Latch
          3. 7.5.8.6.3 Position Counter Initialization
          4. 7.5.8.6.4 eQEP Position-compare Unit
        7. 7.5.8.7  eQEP Edge Capture Unit
        8. 7.5.8.8  eQEP Watchdog
        9. 7.5.8.9  eQEP Unit Timer Base
        10. 7.5.8.10 QMA Module
          1. 7.5.8.10.1 Modes of Operation
            1. 7.5.8.10.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
            2. 7.5.8.10.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
          2. 7.5.8.10.2 Interrupt and Error Generation
        11. 7.5.8.11 eQEP Interrupt Structure
        12. 7.5.8.12 EQEP Programming Guide
      9. 7.5.9  Fast Serial Interface (FSI)
        1. 7.5.9.1 Introduction
          1. 7.5.9.1.1 FSI Features
          2. 7.5.9.1.2 FSI Block Diagram
        2. 7.5.9.2 System-level Integration
          1. 7.5.9.2.1 Signal Description
            1. 7.5.9.2.1.1 Configuring Device Pins
          2. 7.5.9.2.2 FSI Interrupts
            1. 7.5.9.2.2.1 Transmitter Interrupts
            2. 7.5.9.2.2.2 Receiver Interrupts
            3. 7.5.9.2.2.3 Configuring Interrupts
            4. 7.5.9.2.2.4 Handling Interrupts
          3. 7.5.9.2.3 DMA Interface
          4. 7.5.9.2.4 External/PING Trigger Sources
        3. 7.5.9.3 FSI Functional Description
          1. 7.5.9.3.1  Introduction to Operation
          2. 7.5.9.3.2  FSI Transmitter Module
            1. 7.5.9.3.2.1 Initialization
            2. 7.5.9.3.2.2 FSI_TX Clocking
            3. 7.5.9.3.2.3 Transmitting Frames
              1. 7.5.9.3.2.3.1 Software Triggered Frames
              2. 7.5.9.3.2.3.2 Externally Triggered Frames
              3. 7.5.9.3.2.3.3 Ping Frame Generation
                1. 7.5.9.3.2.3.3.1 Automatic Ping Frames
                2. 7.5.9.3.2.3.3.2 Software Triggered Ping Frame
                3. 7.5.9.3.2.3.3.3 Externally Triggered Ping Frame
              4. 7.5.9.3.2.3.4 Transmitting Frames with DMA
            4. 7.5.9.3.2.4 Delay Line Control
            5. 7.5.9.3.2.5 Transmit Buffer Management
            6. 7.5.9.3.2.6 CRC Submodule
            7. 7.5.9.3.2.7 Conditions in Which the Transmitter Must Undergo a Soft Reset
            8. 7.5.9.3.2.8 Reset
          3. 7.5.9.3.3  FSI Receiver Module
            1. 7.5.9.3.3.1  Initialization
            2. 7.5.9.3.3.2  FSI_RX Clocking
            3. 7.5.9.3.3.3  Receiving Frames
              1. 7.5.9.3.3.3.1 Receiving Frames with DMA
            4. 7.5.9.3.3.4  Ping Frame Watchdog
            5. 7.5.9.3.3.5  Frame Watchdog
            6. 7.5.9.3.3.6  Delay Line Control
            7. 7.5.9.3.3.7  Buffer Management
            8. 7.5.9.3.3.8  CRC Submodule
            9. 7.5.9.3.3.9  Using the Zero Bits of the Receiver Tag Registers
            10. 7.5.9.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
            11. 7.5.9.3.3.11 FSI_RX Reset
          4. 7.5.9.3.4  Frame Format
            1. 7.5.9.3.4.1 FSI Frame Phases
            2. 7.5.9.3.4.2 Frame Types
              1. 7.5.9.3.4.2.1 Ping Frames
              2. 7.5.9.3.4.2.2 Error Frames
              3. 7.5.9.3.4.2.3 Data Frames
            3. 7.5.9.3.4.3 Multi-Lane Transmission
          5. 7.5.9.3.5  Flush Sequence
          6. 7.5.9.3.6  FSI Internal Loopback
          7. 7.5.9.3.7  CRC Generation
          8. 7.5.9.3.8  ECC Module
          9. 7.5.9.3.9  FSI Trigger Generation
          10. 7.5.9.3.10 FSI-SPI Compatibility Mode
            1. 7.5.9.3.10.1 Available SPI Modes
              1. 7.5.9.3.10.1.1 FSITX as SPI Controller, Transmit Only
                1. 7.5.9.3.10.1.1.1 Initialization
                2. 7.5.9.3.10.1.1.2 Operation
              2. 7.5.9.3.10.1.2 FSIRX as SPI Peripheral, Receive Only
                1. 7.5.9.3.10.1.2.1 Initialization
                2. 7.5.9.3.10.1.2.2 Operation
              3. 7.5.9.3.10.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
                1. 7.5.9.3.10.1.3.1 Initialization
                2. 7.5.9.3.10.1.3.2 Operation
        4. 7.5.9.4 FSI Programming Guide
          1. 7.5.9.4.1 Establishing the Communication Link
            1. 7.5.9.4.1.1 Establishing the Communication Link from the Main Device
            2. 7.5.9.4.1.2 Establishing the Communication Link from the Remote Device
          2. 7.5.9.4.2 Register Protection
          3. 7.5.9.4.3 Emulation Mode
      10. 7.5.10 Sigma Delta Filter Module (SDFM)
        1. 7.5.10.1  Introduction
          1. 7.5.10.1.1 Features
          2. 7.5.10.1.2 Block Diagram
        2. 7.5.10.2  SDFM Integration
        3. 7.5.10.3  Configuring Device Pins
        4. 7.5.10.4  Input Qualification
        5. 7.5.10.5  Input Control Unit
        6. 7.5.10.6  SDFM Clock Control
        7. 7.5.10.7  Sinc Filter
          1. 7.5.10.7.1 Data Rate and Latency of the Sinc Filter
        8. 7.5.10.8  Data (Primary) Filter Unit
          1. 7.5.10.8.1 32-bit or 16-bit Data Filter Output Representation
          2. 7.5.10.8.2 Data FIFO
          3. 7.5.10.8.3 SDSYNC Event
        9. 7.5.10.9  Comparator (Secondary) Filter Unit
          1. 7.5.10.9.1 Higher Threshold (HLT) Comparators
          2. 7.5.10.9.2 Lower Threshold (LLT) Comparators
          3. 7.5.10.9.3 Digital Filter
        10. 7.5.10.10 Theoretical SDFM Filter Output
        11. 7.5.10.11 Interrupt Unit
          1. 7.5.10.11.1 SDFM (SDy_ERR) Interrupt Sources
          2. 7.5.10.11.2 Data Ready (DRINT) Interrupt Sources
        12. 7.5.10.12 SDFM Programming Guide
      11. 7.5.11 Crossbar (XBAR)
        1. 7.5.11.1 INPUTXBAR
        2. 7.5.11.2 PWMXBAR
        3. 7.5.11.3 MDLXBAR
        4. 7.5.11.4 ICLXBAR
        5. 7.5.11.5 INTXBAR
        6. 7.5.11.6 DMAXBAR
        7. 7.5.11.7 OUTPUTXBAR
          1. 7.5.11.7.1 OUTPUTXBAR Input Connection Table
        8. 7.5.11.8 PWMSYNCOUTXBAR
        9. 7.5.11.9 XBAR Programming Guide
    6. 7.6 OptiFlash
      1. 7.6.1 OptiFlash Overview
      2. 7.6.2 OptiFlash Components
        1. 7.6.2.1 Octal Serial Peripheral Interface (OSPI)
        2. 7.6.2.2 Remote Layer 2 Cache (RL2)
        3. 7.6.2.3 Fast Local Copy (FLC)
        4. 7.6.2.4 On-the-Fly Authentication (OTFA)
        5. 7.6.2.5 Region Address Translation (RAT)
        6. 7.6.2.6 Firmware Upgrade Over the Air (FOTA)
  10. 8 Interprocessor Communication (IPC)
    1. 8.1 Mailbox
      1. 8.1.1 Mailbox
      2. 8.1.2 Maibox Message Scheme
      3. 8.1.3 Maibox Message Example
      4. 8.1.4 Maibox Registers
        1. 8.1.4.1 R5SS0_CORE0 Mailbox Registers
        2. 8.1.4.2 R5SS0_CORE1 Mailbox Registers
        3. 8.1.4.3 R5SS1_CORE0 Mailbox Registers
        4. 8.1.4.4 R5SS1_CORE1 Mailbox Registers
        5. 8.1.4.5 ICSSM_PRU0 Mailbox Registers
        6. 8.1.4.6 ICSSM_PRU1 Mailbox Registers
        7. 8.1.4.7 HSM Mailbox Registers
    2. 8.2 Spinlock
      1. 8.2.1 Spinlock Overview
        1. 8.2.1.1 Spinlock Not Supported Features
      2. 8.2.2 Spinlock Integration
        1.       Spinlock Integration
      3. 8.2.3 Spinlock Functional Description
        1. 8.2.3.1 Spinlock Software Reset
        2. 8.2.3.2 About Spinlocks
        3. 8.2.3.3 Spinlock Functional Operation
      4. 8.2.4 Spinlock Programming Guide
        1. 8.2.4.1 Spinlock Low-level Programming Models
          1. 8.2.4.1.1 Basic Spinlock Operations
            1. 8.2.4.1.1.1 Spinlocks Clearing After a System Bug Recovery
            2. 8.2.4.1.1.2 Take and Release Spinlock
  11. 9 Memory Controllers
    1. 9.1 Memory Controllers Overview
  12. 10Interrupts
    1. 10.1 Interrupt Architecture
    2. 10.2 Interrupt Controllers
      1. 10.2.1 Vectored Interrupt Manager (VIM)
        1. 10.2.1.1 VIM Overview
        2. 10.2.1.2 VIM Interrupt Inputs
        3. 10.2.1.3 VIM Interrupt Outputs
        4. 10.2.1.4 VIM Interrupt Vector Table (VIM RAM)
        5. 10.2.1.5 VIM Interrupt Prioritization
        6. 10.2.1.6 VIM ECC Support
        7. 10.2.1.7 VIM IDLE State
        8. 10.2.1.8 VIM Interrupt Handling
          1. 10.2.1.8.1 Servicing IRQ Through Vector Interface
          2. 10.2.1.8.2 Servicing IRQ Through MMR Interface
          3. 10.2.1.8.3 Servicing IRQ Through MMR Interface (Alternative)
          4. 10.2.1.8.4 Servicing FIQ
          5. 10.2.1.8.5 Servicing FIQ (Alternative)
      2. 10.2.2 Other Interrupt Controllers
    3. 10.3 Interrupt Routers
      1. 10.3.1 INTRTR Overview
      2. 10.3.2 INTRTR Integration
        1. 10.3.2.1 PRU-ICSS XBAR INTRTR0
        2. 10.3.2.2 EDMA XBAR INTRTR0
        3. 10.3.2.3 GPIO XBAR INTRTR0
    4. 10.4 Interrupt Sources
      1. 10.4.1 R5FSS0_CORE0 Interrupt Map
      2. 10.4.2 R5FSS0_CORE1 Interrupt Map
      3. 10.4.3 R5FSS1_CORE0 Interrupt Map
      4. 10.4.4 R5FSS1_CORE1 Interrupt Map
      5. 10.4.5 PRU-ICSS Interrupt Map
      6. 10.4.6 ESM0 Interrupt Map
  13. 11Data Movement Architecture
    1. 11.1 Data Movement Architecture Overview
      1. 11.1.1 Overview
      2. 11.1.2 Definition of Terms
    2. 11.2 Enhanced Direct Memory Access (EDMA)
      1. 11.2.1 EDMA Module Overview
        1. 11.2.1.1 EDMA Features
      2. 11.2.2 EDMA Integration
        1. 11.2.2.1 EDMA Integration
        2. 11.2.2.2 EDMA Interrupt Aggregator
        3. 11.2.2.3 EDMA Error Interrupt Aggregator
        4. 11.2.2.4 EDMA Configuration
      3. 11.2.3 EDMA Controller Functional Description
        1. 11.2.3.1  Block Diagram
          1. 11.2.3.1.1 Third-Party Channel Controller
          2. 11.2.3.1.2 Third-Party Transfer Controller
        2. 11.2.3.2  Types of EDMA Controller Transfers
          1. 11.2.3.2.1 A-Synchronized Transfers
          2. 11.2.3.2.2 AB-Synchronized Transfers
        3. 11.2.3.3  Parameter RAM (PaRAM)
          1. 11.2.3.3.1 PaRAM
          2. 11.2.3.3.2 EDMA Channel PaRAM Set Entry Fields
            1. 11.2.3.3.2.1  Channel Options Parameter (OPT)
            2. 11.2.3.3.2.2  Channel Source Address (SRC)
            3. 11.2.3.3.2.3  Channel Destination Address (DST)
            4. 11.2.3.3.2.4  Count for 1st Dimension (ACNT)
            5. 11.2.3.3.2.5  Count for 2nd Dimension (BCNT)
            6. 11.2.3.3.2.6  Count for 3rd Dimension (CCNT)
            7. 11.2.3.3.2.7  BCNT Reload (BCNTRLD)
            8. 11.2.3.3.2.8  Source B Index (SBIDX)
            9. 11.2.3.3.2.9  Destination B Index (DBIDX)
            10. 11.2.3.3.2.10 Source C Index (SCIDX)
            11. 11.2.3.3.2.11 Destination C Index (DCIDX)
            12. 11.2.3.3.2.12 Link Address (LINK)
          3. 11.2.3.3.3 Null PaRAM Set
          4. 11.2.3.3.4 Dummy PaRAM Set
          5. 11.2.3.3.5 Dummy Versus Null Transfer Comparison
          6. 11.2.3.3.6 Parameter Set Updates
          7. 11.2.3.3.7 Linking Transfers
          8. 11.2.3.3.8 Constant Addressing Mode Transfers/Alignment Issues
          9. 11.2.3.3.9 Element Size
        4. 11.2.3.4  Initiating a DMA Transfer
          1. 11.2.3.4.1 DMA Channels
            1. 11.2.3.4.1.1 Event-Triggered Transfer Request
            2. 11.2.3.4.1.2 Manually-Triggered Transfer Request
            3. 11.2.3.4.1.3 Chain-Triggered Transfer Request
          2. 11.2.3.4.2 QDMA Channels
            1. 11.2.3.4.2.1 Auto-Triggered and Link-Triggered Transfer Request
          3. 11.2.3.4.3 Comparison Between DMA and QDMA Channels
        5. 11.2.3.5  Completion of a DMA Transfer
          1. 11.2.3.5.1 Normal Completion
          2. 11.2.3.5.2 Early Completion
          3. 11.2.3.5.3 Dummy or Null Completion
        6. 11.2.3.6  Event, Channel, and PaRAM Mapping
          1. 11.2.3.6.1 DMA Channel to PaRAM Mapping
          2. 11.2.3.6.2 QDMA Channel to PaRAM Mapping
        7. 11.2.3.7  EDMA Channel Controller Regions
          1. 11.2.3.7.1 Region Overview
          2. 11.2.3.7.2 Channel Controller Regions
            1. 11.2.3.7.2.1 Resource Pool Division Across Two Regions
          3. 11.2.3.7.3 Region Interrupts
        8. 11.2.3.8  Chaining EDMA Channels
        9. 11.2.3.9  EDMA Interrupts
          1. 11.2.3.9.1 Transfer Completion Interrupts
            1. 11.2.3.9.1.1 Enabling Transfer Completion Interrupts
            2. 11.2.3.9.1.2 Clearing Transfer Completion Interrupts
          2. 11.2.3.9.2 EDMA Interrupt Servicing
          3. 11.2.3.9.3 Interrupt Servicing
          4. 11.2.3.9.4 1222
          5. 11.2.3.9.5 Interrupt Servicing
          6. 11.2.3.9.6 Interrupt Evaluation Operations
          7. 11.2.3.9.7 Error Interrupts
        10. 11.2.3.10 Memory Protection
          1. 11.2.3.10.1 Active Memory Protection
          2. 11.2.3.10.2 Proxy Memory Protection
        11. 11.2.3.11 Event Queue(s)
          1. 11.2.3.11.1 DMA/QDMA Channel to Event Queue Mapping
          2. 11.2.3.11.2 Queue RAM Debug Visibility
          3. 11.2.3.11.3 Queue Resource Tracking
          4. 11.2.3.11.4 Performance Considerations
        12. 11.2.3.12 EDMA Transfer Controller (EDMA_TPTC)
          1. 11.2.3.12.1 Architecture Details
            1. 11.2.3.12.1.1 Command Fragmentation
            2. 11.2.3.12.1.2 TR Pipelining
            3. 11.2.3.12.1.3 Command Fragmentation (DBS = 64)
            4. 11.2.3.12.1.4 Performance Tuning
          2. 11.2.3.12.2 Memory Protection
          3. 11.2.3.12.3 Error Generation
          4. 11.2.3.12.4 Debug Features
            1. 11.2.3.12.4.1 Destination FIFO Register Pointer
        13. 11.2.3.13 Event Dataflow
        14. 11.2.3.14 EDMA Controller Prioritization
          1. 11.2.3.14.1 Channel Priority
          2. 11.2.3.14.2 Trigger Source Priority
          3. 11.2.3.14.3 Dequeue Priority
        15. 11.2.3.15 Emulation Considerations
      4. 11.2.4 EDMA Transfer Examples
        1. 11.2.4.1 Block Move Example
        2. 11.2.4.2 Subframe Extraction Example
        3. 11.2.4.3 Data Sorting Example
        4. 11.2.4.4 Setting Up an EDMA Transfer
      5. 11.2.5 EDMA Debug Checklist and Programming Tips
        1. 11.2.5.1 EDMA Debug Checklist
        2. 11.2.5.2 EDMA Programming Tips
      6. 11.2.6 EDMA Event Map
  14. 12Time Sync
    1. 12.1 Time Sync Architecture
      1. 12.1.1 Time Sync Architecture Overview
    2. 12.2 Time Sync Routers
      1. 12.2.1 Time Sync Routers Overview
        1. 12.2.1.1 SOC_TIMESYNC_XBAR0 Overview
        2. 12.2.1.2 SOC_TIMESYNC_XBAR1 Overview
      2. 12.2.2 Time Sync Routers Integration
        1. 12.2.2.1 SOC_TIMESYNC_XBAR0 Integration
        2. 12.2.2.2 SOC_TIMESYNC_XBAR1 Integration
      3. 12.2.3 Time Sync Routers Registers
        1. 12.2.3.1 SOC_TIMESYNC_XBAR0 Registers
        2. 12.2.3.2 SOC_TIMESYNC_XBAR1 Registers
    3. 12.3 Time Sync and Compare Events
      1. 12.3.1 TimeSync Event Sources
        1. 12.3.1.1 SOC_TIMESYNC_XBAR0 Event Map
        2. 12.3.1.2 SOC_TIMESYNC_XBAR1 Event Map
        3. 12.3.1.3 PRU-ICSS Event Map
        4. 12.3.1.4 CPSW0_CPTS Event Map
  15. 13Peripherals
    1. 13.1 General Connectivity Peripherals
      1. 13.1.1 General-Purpose Interface (GPIO)
        1. 13.1.1.1 GPIO Overview
        2. 13.1.1.2 GPIO Environment
        3. 13.1.1.3 GPIO Integration
        4. 13.1.1.4 GPIO Functional Description
          1. 13.1.1.4.1 GPIO Block Diagram
          2. 13.1.1.4.2 GPIO Function
          3. 13.1.1.4.3 GPIO Interrupt and Event Generation
            1. 13.1.1.4.3.1 Interrupt Enable (per Bank)
            2. 13.1.1.4.3.2 Trigger Configuration (per Bit)
            3. 13.1.1.4.3.3 Interrupt Status and Clear (per Bit)
          4. 13.1.1.4.4 Input Qualification
            1. 13.1.1.4.4.1 No Synchronization (Asynchronous Input)
            2. 13.1.1.4.4.2 Synchronization to SYSCLK Only
            3. 13.1.1.4.4.3 Qualification Using a Sampling Window
          5. 13.1.1.4.5 GPIO Interrupt Connectivity
          6. 13.1.1.4.6 GPIO Emulation Halt Operation
      2. 13.1.2 Inter-Integrated Circuit (I2C) Interface
        1. 13.1.2.1 I2C Overview
          1. 13.1.2.1.1 I2C Features
          2. 13.1.2.1.2 I2C Not Supported Features
        2. 13.1.2.2 I2C Environment
          1. 13.1.2.2.1 I2C Typical Application
            1. 13.1.2.2.1.1 I2C Interface Typical Connections
            2. 13.1.2.2.1.2 1304
          2. 13.1.2.2.2 I2C Typical Connection Protocol and Data Format
            1. 13.1.2.2.2.1  I2C Serial Data Formats
            2. 13.1.2.2.2.2  I2C Data Validity
            3. 13.1.2.2.2.3  I2C Start and Stop Conditions
            4. 13.1.2.2.2.4  I2C Addressing
              1. 13.1.2.2.2.4.1 7-Bit Addressing Format
              2. 13.1.2.2.2.4.2 10-Bit Addressing Format
              3. 13.1.2.2.2.4.3 Using the Repeated START Condition
              4. 13.1.2.2.2.4.4 Free Data Format
            5. 13.1.2.2.2.5  I2C Controller Transmitter
            6. 13.1.2.2.2.6  I2C Controller Receiver
            7. 13.1.2.2.2.7  I2C Target Transmitter
            8. 13.1.2.2.2.8  I2C Target Receiver
            9. 13.1.2.2.2.9  I2C Bus Arbitration
            10. 13.1.2.2.2.10 I2C Clock Generation and Synchronization
        3. 13.1.2.3 I2C Integration
        4. 13.1.2.4 I2C Functional Description
          1. 13.1.2.4.1 I2C Block Diagram
          2. 13.1.2.4.2 I2C Clocks
            1. 13.1.2.4.2.1 I2C Clocking
          3. 13.1.2.4.3 I2C Software Reset
          4. 13.1.2.4.4 I2C Interrupt Requests
          5. 13.1.2.4.5 I2C Noise Filter
        5. 13.1.2.5 I2C Programming Guide
          1. 13.1.2.5.1 I2C Low-Level Programming Models
            1. 13.1.2.5.1.1 I2C Programming Model
              1. 13.1.2.5.1.1.1 Main Program
                1. 13.1.2.5.1.1.1.1 Module State after Reset
                2. 13.1.2.5.1.1.1.2 Initialization Procedure
                3. 13.1.2.5.1.1.1.3 Section
                4. 13.1.2.5.1.1.1.4 Configure Address Registers
                5. 13.1.2.5.1.1.1.5 Initiate a Transfer
                6. 13.1.2.5.1.1.1.6 Receive Data
                7. 13.1.2.5.1.1.1.7 Transmit Data
              2. 13.1.2.5.1.1.2 Interrupt Subroutine Sequence
      3. 13.1.3 Multichannel Serial Peripheral Interface (MCSPI)
        1. 13.1.3.1 MCSPI Overview
          1. 13.1.3.1.1 SPI Features
          2. 13.1.3.1.2 SPI Not Supported Features
        2. 13.1.3.2 SPI Environment
          1. 13.1.3.2.1 MCSPI Protocol and Data Format
            1. 13.1.3.2.1.1 Transfer Format
          2. 13.1.3.2.2 MCSPI in Controller Mode
          3. 13.1.3.2.3 MCSPI in Peripheral Mode
        3. 13.1.3.3 SPI Integration
        4. 13.1.3.4 MCSPI Functional Description
          1. 13.1.3.4.1 SPI Block Diagram
          2. 13.1.3.4.2 MCSPI Reset
          3. 13.1.3.4.3 MCSPI Controller Mode
            1. 13.1.3.4.3.1 Controller Mode Features
            2. 13.1.3.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 13.1.3.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 13.1.3.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 13.1.3.4.3.5 Single-Channel Controller Mode
              1. 13.1.3.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 13.1.3.4.3.5.2 Force SPIEN[i] Mode
              3. 13.1.3.4.3.5.3 Turbo Mode
            6. 13.1.3.4.3.6 Start-Bit Mode
            7. 13.1.3.4.3.7 Chip-Select Timing Control
            8. 13.1.3.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 13.1.3.4.3.8.1 Clock Ratio Granularity
          4. 13.1.3.4.4 MCSPI Peripheral Mode
            1. 13.1.3.4.4.1 Dedicated Resources
            2. 13.1.3.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 13.1.3.4.4.3 Peripheral Transmit-Only Mode
            4. 13.1.3.4.4.4 Peripheral Receive-Only Mode
          5. 13.1.3.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 13.1.3.4.6 MCSPI FIFO Buffer Management
            1. 13.1.3.4.6.1 Buffer Almost Full
            2. 13.1.3.4.6.2 Buffer Almost Empty
            3. 13.1.3.4.6.3 End of Transfer Management
            4. 13.1.3.4.6.4 Multiple MCSPI Word Access
            5. 13.1.3.4.6.5 First MCSPI Word Delay
          7. 13.1.3.4.7 MCSPI Interrupts
            1. 13.1.3.4.7.1 Interrupt Events in Controller Mode
              1. 13.1.3.4.7.1.1 TXx_EMPTY
              2. 13.1.3.4.7.1.2 TXx_UNDERFLOW
              3. 13.1.3.4.7.1.3 RXx_ FULL
              4. 13.1.3.4.7.1.4 End Of Word Count
            2. 13.1.3.4.7.2 Interrupt Events in Peripheral Mode
              1. 13.1.3.4.7.2.1 TXx_EMPTY
              2. 13.1.3.4.7.2.2 TXx_UNDERFLOW
              3. 13.1.3.4.7.2.3 RXx_FULL
              4. 13.1.3.4.7.2.4 RX0_OVERFLOW
              5. 13.1.3.4.7.2.5 End Of Word Count
            3. 13.1.3.4.7.3 Interrupt-Driven Operation
            4. 13.1.3.4.7.4 Polling
          8. 13.1.3.4.8 MCSPI DMA Requests
        5. 13.1.3.5 MCSPI Programming Guide
          1. 13.1.3.5.1 MCSPI Global Initialization
            1. 13.1.3.5.1.1 MCSPI Global Initialization
              1. 13.1.3.5.1.1.1 Main Sequence – MCSPI Global Initialization
          2. 13.1.3.5.2 MCSPI Operational Mode Configuration
            1. 13.1.3.5.2.1 MCSPI Operational Modes
              1. 13.1.3.5.2.1.1 Common Transfer Sequence
              2. 13.1.3.5.2.1.2 End of Transfer Sequences
              3. 13.1.3.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 13.1.3.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 13.1.3.5.2.1.4.1 Based on Interrupt Requests
                2. 13.1.3.5.2.1.4.2 Based on DMA Write Requests
              5. 13.1.3.5.2.1.5 Controller Normal Receive-Only
                1. 13.1.3.5.2.1.5.1 Based on Interrupt Requests
                2. 13.1.3.5.2.1.5.2 Based on DMA Read Requests
              6. 13.1.3.5.2.1.6 Controller Turbo Receive-Only
                1. 13.1.3.5.2.1.6.1 Based on Interrupt Requests
                2. 13.1.3.5.2.1.6.2 Based on DMA Read Requests
              7. 13.1.3.5.2.1.7 Peripheral Receive-Only
              8. 13.1.3.5.2.1.8 Transfer Procedures With FIFO
                1. 13.1.3.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 13.1.3.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 13.1.3.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 13.1.3.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 13.1.3.5.2.1.8.5 Transmit-Only
                6. 13.1.3.5.2.1.8.6 Receive-Only With Word Count
                7. 13.1.3.5.2.1.8.7 Receive-Only Without Word Count
              9. 13.1.3.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 13.1.3.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 13.1.3.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 13.1.3.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 13.1.3.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
          3. 13.1.3.5.3 Common Transfer Procedures Without FIFO – Polling Method
            1. 13.1.3.5.3.1 Receive-Only Procedure – Polling Method
            2. 13.1.3.5.3.2 Receive-Only Procedure – Interrupt Method
            3. 13.1.3.5.3.3 Transmit-Only Procedure – Polling Method
            4. 13.1.3.5.3.4 Transmit-and-Receive Procedure – Polling Method
      4. 13.1.4 Universal Asynchronous Receiver/Transmitter (UART)
        1. 13.1.4.1 UART Overview
          1. 13.1.4.1.1 UART Features
          2. 13.1.4.1.2 IrDA Features
          3. 13.1.4.1.3 CIR Features
          4. 13.1.4.1.4 ISO 7816 (Smartcard) Functions
        2. 13.1.4.2 UART Environment
          1. 13.1.4.2.1 UART Functional Interfaces
            1. 13.1.4.2.1.1 System Using UART Communication With Hardware Handshake
            2. 13.1.4.2.1.2 UART Interface Description
            3. 13.1.4.2.1.3 UART Protocol and Data Format
          2. 13.1.4.2.2 RS-485 Functional Interfaces
            1. 13.1.4.2.2.1 System Using RS-485 Communication
            2. 13.1.4.2.2.2 RS-485 Interface Description
          3. 13.1.4.2.3 IrDA Functional Interfaces
            1. 13.1.4.2.3.1 System Using IrDA Communication Protocol
            2. 13.1.4.2.3.2 IrDA Interface Description
            3. 13.1.4.2.3.3 IrDA Protocol and Data Format
              1. 13.1.4.2.3.3.1 SIR Mode
                1. 13.1.4.2.3.3.1.1 Frame Format
                2. 13.1.4.2.3.3.1.2 Asynchronous Transparency
                3. 13.1.4.2.3.3.1.3 Abort Sequence
                4. 13.1.4.2.3.3.1.4 Pulse Shaping
                5. 13.1.4.2.3.3.1.5 Encoder
                6. 13.1.4.2.3.3.1.6 Decoder
                7. 13.1.4.2.3.3.1.7 IR Address Checking
              2. 13.1.4.2.3.3.2 SIR Free-Format Mode
              3. 13.1.4.2.3.3.3 MIR Mode
                1. 13.1.4.2.3.3.3.1 MIR Encoder/Decoder
                2. 13.1.4.2.3.3.3.2 SIP Generation
              4. 13.1.4.2.3.3.4 FIR Mode
          4. 13.1.4.2.4 CIR Functional Interfaces
            1. 13.1.4.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 13.1.4.2.4.2 CIR Interface Description
            3. 13.1.4.2.4.3 CIR Protocol and Data Format
              1. 13.1.4.2.4.3.1 Carrier Modulation
              2. 13.1.4.2.4.3.2 Pulse Duty Cycle
              3. 13.1.4.2.4.3.3 Consumer IR Encoding/Decoding
        3. 13.1.4.3 UART Integration
        4. 13.1.4.4 UART Functional Description
          1. 13.1.4.4.1 UART Block Diagram
          2. 13.1.4.4.2 UART Clock Configuration
          3. 13.1.4.4.3 UART Software Reset
            1. 13.1.4.4.3.1 Independent TX/RX
          4. 13.1.4.4.4 UART Power Management
            1. 13.1.4.4.4.1 UART Mode Power Management
              1. 13.1.4.4.4.1.1 Module Power Saving
              2. 13.1.4.4.4.1.2 System Power Saving
            2. 13.1.4.4.4.2 IrDA Mode Power Management
              1. 13.1.4.4.4.2.1 Module Power Saving
              2. 13.1.4.4.4.2.2 System Power Saving
            3. 13.1.4.4.4.3 CIR Mode Power Management
              1. 13.1.4.4.4.3.1 Module Power Saving
              2. 13.1.4.4.4.3.2 System Power Saving
            4. 13.1.4.4.4.4 Local Power Management
          5. 13.1.4.4.5 UART Interrupt Requests
            1. 13.1.4.4.5.1 UART Mode Interrupt Management
              1. 13.1.4.4.5.1.1 UART Interrupts
              2. 13.1.4.4.5.1.2 Wake-Up Interrupt
            2. 13.1.4.4.5.2 IrDA Mode Interrupt Management
              1. 13.1.4.4.5.2.1 IrDA Interrupts
              2. 13.1.4.4.5.2.2 Wake-Up Interrupts
            3. 13.1.4.4.5.3 CIR Mode Interrupt Management
              1. 13.1.4.4.5.3.1 CIR Interrupts
              2. 13.1.4.4.5.3.2 Wake-Up Interrupts
          6. 13.1.4.4.6 UART FIFO Management
            1. 13.1.4.4.6.1 FIFO Trigger
              1. 13.1.4.4.6.1.1 Transmit FIFO Trigger
              2. 13.1.4.4.6.1.2 Receive FIFO Trigger
            2. 13.1.4.4.6.2 FIFO Interrupt Mode
            3. 13.1.4.4.6.3 FIFO Polled Mode Operation
            4. 13.1.4.4.6.4 FIFO DMA Mode Operation
              1. 13.1.4.4.6.4.1 DMA sequence to disable TX DMA
              2. 13.1.4.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 13.1.4.4.6.4.3 DMA Transmission
              4. 13.1.4.4.6.4.4 DMA Reception
          7. 13.1.4.4.7 UART Mode Selection
            1. 13.1.4.4.7.1 Register Access Modes
              1. 13.1.4.4.7.1.1 Operational Mode and Configuration Modes
              2. 13.1.4.4.7.1.2 Register Access Submode
              3. 13.1.4.4.7.1.3 Registers Available for the Register Access Modes
            2. 13.1.4.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 13.1.4.4.7.2.1 Registers Available for the UART Function
              2. 13.1.4.4.7.2.2 Registers Available for the IrDA Function
              3. 13.1.4.4.7.2.3 Registers Available for the CIR Function
          8. 13.1.4.4.8 UART Protocol Formatting
            1. 13.1.4.4.8.1 UART Mode
              1. 13.1.4.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 13.1.4.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 13.1.4.4.8.1.3 Multi-drop Parity Mode with Address Match
              4. 13.1.4.4.8.1.4 Time-guard
              5. 13.1.4.4.8.1.5 UART Data Formatting
                1. 13.1.4.4.8.1.5.1 Frame Formatting
                2. 13.1.4.4.8.1.5.2 Hardware Flow Control
                3. 13.1.4.4.8.1.5.3 Software Flow Control
                  1. 1.4.4.8.1.5.3.1 Receive (RX)
                  2. 1.4.4.8.1.5.3.2 Transmit (TX)
                4. 13.1.4.4.8.1.5.4 Autobauding Modes
                5. 13.1.4.4.8.1.5.5 Error Detection
                6. 13.1.4.4.8.1.5.6 Overrun During Receive
                7. 13.1.4.4.8.1.5.7 Time-Out and Break Conditions
                  1. 1.4.4.8.1.5.7.1 Time-Out Counter
                  2. 1.4.4.8.1.5.7.2 Break Condition
            2. 13.1.4.4.8.2 RS-485 Mode
              1. 13.1.4.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 13.1.4.4.8.3 IrDA Mode
              1. 13.1.4.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 13.1.4.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 13.1.4.4.8.3.3 IrDA Data Formatting
                1. 13.1.4.4.8.3.3.1 IR RX Polarity Control
                2. 13.1.4.4.8.3.3.2 IrDA Reception Control
                3. 13.1.4.4.8.3.3.3 IR Address Checking
                4. 13.1.4.4.8.3.3.4 Frame Closing
                5. 13.1.4.4.8.3.3.5 Store and Controlled Transmission
                6. 13.1.4.4.8.3.3.6 Error Detection
                7. 13.1.4.4.8.3.3.7 Underrun During Transmission
                8. 13.1.4.4.8.3.3.8 Overrun During Receive
                9. 13.1.4.4.8.3.3.9 Status FIFO
              4. 13.1.4.4.8.3.4 SIR Mode Data Formatting
                1. 13.1.4.4.8.3.4.1 Abort Sequence
                2. 13.1.4.4.8.3.4.2 Pulse Shaping
                3. 13.1.4.4.8.3.4.3 SIR Free Format Programming
              5. 13.1.4.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 13.1.4.4.8.4 CIR Mode
              1. 13.1.4.4.8.4.1 CIR Mode Clock Generation
              2. 13.1.4.4.8.4.2 CIR Data Formatting
                1. 13.1.4.4.8.4.2.1 IR RX Polarity Control
                2. 13.1.4.4.8.4.2.2 CIR Transmission
                3. 13.1.4.4.8.4.2.3 CIR Reception
        5. 13.1.4.5 UART Programming Guide
          1. 13.1.4.5.1 UART Global Initialization
            1. 13.1.4.5.1.1 Surrounding Modules Global Initialization
            2. 13.1.4.5.1.2 UART Module Global Initialization
          2. 13.1.4.5.2 UART Mode selection
          3. 13.1.4.5.3 UART Submode selection
          4. 13.1.4.5.4 UART Load FIFO trigger and DMA mode settings
            1. 13.1.4.5.4.1 DMA mode Settings
            2. 13.1.4.5.4.2 FIFO Trigger Settings
          5. 13.1.4.5.5 UART Protocol, Baud rate and interrupt settings
            1. 13.1.4.5.5.1 Baud rate settings
            2. 13.1.4.5.5.2 Interrupt settings
            3. 13.1.4.5.5.3 Protocol settings
            4. 13.1.4.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 13.1.4.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 13.1.4.5.6 UART Hardware and Software Flow Control Configuration
            1. 13.1.4.5.6.1 Hardware Flow Control Configuration
            2. 13.1.4.5.6.2 Software Flow Control Configuration
          7. 13.1.4.5.7 IrDA Programming Model
            1. 13.1.4.5.7.1 SIR mode
              1. 13.1.4.5.7.1.1 Receive
              2. 13.1.4.5.7.1.2 Transmit
            2. 13.1.4.5.7.2 MIR mode
              1. 13.1.4.5.7.2.1 Receive
              2. 13.1.4.5.7.2.2 Transmit
            3. 13.1.4.5.7.3 FIR mode
              1. 13.1.4.5.7.3.1 Receive
              2. 13.1.4.5.7.3.2 Transmit
    2. 13.2 High-speed Serial Interfaces
      1. 13.2.1 Gigabit Ethernet Switch (CPSW)
        1. 13.2.1.1 CPSW0 Overview
          1. 13.2.1.1.1 CPSW0 Features
          2. 13.2.1.1.2 CPSW0 Not Supported Features
          3. 13.2.1.1.3 CPSW Terminology
        2. 13.2.1.2 CPSW0 Environment
          1. 13.2.1.2.1 CPSW0 MII Interface
          2. 13.2.1.2.2 CPSW0 RMII Interface
          3. 13.2.1.2.3 CPSW0 RGMII Interface
        3. 13.2.1.3 CPSW Integration
        4. 13.2.1.4 CPSW0 Functional Description
          1. 13.2.1.4.1  Functional Block Diagram
          2. 13.2.1.4.2  CPSW Ports
            1. 13.2.1.4.2.1 Interface Mode Selection
          3. 13.2.1.4.3  Clocking
            1. 13.2.1.4.3.1 Subsystem Clocking
            2. 13.2.1.4.3.2 Interface Clocking
              1. 13.2.1.4.3.2.1 RGMII Interface Clocking
              2. 13.2.1.4.3.2.2 RMII Interface Clocking
              3. 13.2.1.4.3.2.3 MDIO Clocking
          4. 13.2.1.4.4  Software IDLE
          5. 13.2.1.4.5  Interrupt Functionality
          6. 13.2.1.4.6  CPSW
            1. 13.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 13.2.1.4.6.1.1  Error Handling
              2. 13.2.1.4.6.1.2  Bypass Operations
              3. 13.2.1.4.6.1.3  OUI Deny or Accept
              4. 13.2.1.4.6.1.4  Statistics Counting
              5. 13.2.1.4.6.1.5  Automotive Security Features
              6. 13.2.1.4.6.1.6  CPSW Switching Solutions
                1. 13.2.1.4.6.1.6.1 Basics of 3-port Switch Type
              7. 13.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 13.2.1.4.6.1.7.1 InterVLAN Routing
                2. 13.2.1.4.6.1.7.2 OAM Operations
              8. 13.2.1.4.6.1.8  Supervisory packets
              9. 13.2.1.4.6.1.9  Address Table Entry
                1. 13.2.1.4.6.1.9.1  Free Table Entry
                2. 13.2.1.4.6.1.9.2  OUI Unicast Address Table Entry
                3. 13.2.1.4.6.1.9.3  Unicast Address Table Entry (Bit 40 == 0)
                4. 13.2.1.4.6.1.9.4  Multicast Address Table Entry (Bit 40==1)
                5. 13.2.1.4.6.1.9.5  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                6. 13.2.1.4.6.1.9.6  VLAN/Multicast Address Table Entry (Bit 40==1)
                7. 13.2.1.4.6.1.9.7  Inner VLAN Table Entry
                8. 13.2.1.4.6.1.9.8  Outer VLAN Table Entry
                9. 13.2.1.4.6.1.9.9  EtherType Table Entry
                10. 13.2.1.4.6.1.9.10 IPv4 Table Entry
                11. 13.2.1.4.6.1.9.11 IPv6 Table Entries
                  1. 2.1.4.6.1.9.11.1 IPv6 Table Entry High
                  2. 2.1.4.6.1.9.11.2 IPv6 Table Entry Low
              10. 13.2.1.4.6.1.10 Multicast Address
                1. 13.2.1.4.6.1.10.1 Multicast Ranges
              11. 13.2.1.4.6.1.11 Aging and Auto Aging
              12. 13.2.1.4.6.1.12 ALE Policing and Classification
                1. 13.2.1.4.6.1.12.1 ALE Policing
                2. 13.2.1.4.6.1.12.2 Classifier to Host Thread Mapping
                3. 13.2.1.4.6.1.12.3 ALE Classification
              13. 13.2.1.4.6.1.13 Mirroring
              14. 13.2.1.4.6.1.14 Trunking
              15. 13.2.1.4.6.1.15 DSCP
              16. 13.2.1.4.6.1.16 Packet Forwarding Processes
                1. 13.2.1.4.6.1.16.1 Ingress Filtering Process
                2. 13.2.1.4.6.1.16.2 VLAN Lookup Process
                3. 13.2.1.4.6.1.16.3 Egress Process
                4. 13.2.1.4.6.1.16.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.16.4.1 Learning Process
                  2. 2.1.4.6.1.16.4.2 Updating Process
                  3. 2.1.4.6.1.16.4.3 Touching Process
              17. 13.2.1.4.6.1.17 VLAN Aware Mode
              18. 13.2.1.4.6.1.18 VLAN Unaware Mode
              19. 13.2.1.4.6.1.19 Transmit VLAN Processing
                1. 13.2.1.4.6.1.19.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 13.2.1.4.6.1.19.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 13.2.1.4.6.1.19.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
            2. 13.2.1.4.6.2  Packet Priority Handling
              1. 13.2.1.4.6.2.1 Ethernet Port Receive
              2. 13.2.1.4.6.2.2 CPDMA Port Receive
              3. 13.2.1.4.6.2.3 CPDMA Port Transmit
              4. 13.2.1.4.6.2.4 Priority Mapping and Transmit VLAN Priority
            3. 13.2.1.4.6.3  CPPI Port Ingress
            4. 13.2.1.4.6.4  Packet CRC Handling
              1. 13.2.1.4.6.4.1 Ethernet Port Ingress Packet CRC
              2. 13.2.1.4.6.4.2 Ethernet Port Egress Packet CRC
              3. 13.2.1.4.6.4.3 CPPI Port Ingress Packet CRC
              4. 13.2.1.4.6.4.4 CPPI Port Egress Packet CRC
            5. 13.2.1.4.6.5  FIFO Memory Control
            6. 13.2.1.4.6.6  FIFO Transmit Queue Control
            7. 13.2.1.4.6.7  Rate Limiting (Traffic Shaping)
              1. 13.2.1.4.6.7.1 CPPI Port Receive Rate Limiting
              2. 13.2.1.4.6.7.2 Ethernet Port Transmit Rate Limiting
            8. 13.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 13.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 13.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 13.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 13.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 13.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 13.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 13.2.1.4.6.9  Audio Video Bridging
              1. 13.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 13.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 13.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 13.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 13.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 13.2.1.4.6.10 Ethernet MAC Sliver
              1. 13.2.1.4.6.10.1 Ethernet MAC Sliver Overview
                1. 13.2.1.4.6.10.1.1 CRC Insertion
                2. 13.2.1.4.6.10.1.2 MTXER
                3. 13.2.1.4.6.10.1.3 Adaptive Performance Optimization (APO)
                4. 13.2.1.4.6.10.1.4 Inter-Packet-Gap Enforcement
                5. 13.2.1.4.6.10.1.5 Back Off
                6. 13.2.1.4.6.10.1.6 Programmable Transmit Inter-Packet Gap
                7. 13.2.1.4.6.10.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 13.2.1.4.6.10.2 RMII Interface
                1. 13.2.1.4.6.10.2.1 Features
                2. 13.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 13.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 13.2.1.4.6.10.3 RGMII Interface
                1. 13.2.1.4.6.10.3.1 Features
                2. 13.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 13.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 13.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 13.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 13.2.1.4.6.10.4 Frame Classification
              5. 13.2.1.4.6.10.5 Receive FIFO Architecture
            11. 13.2.1.4.6.11 Embedded Memories
            12. 13.2.1.4.6.12 Memory Error Detection and Correction
              1. 13.2.1.4.6.12.1 Packet Header ECC
              2. 13.2.1.4.6.12.2 Packet Protect CRC
              3. 13.2.1.4.6.12.3 Aggregator RAM Control
            13. 13.2.1.4.6.13 Ethernet Port Flow Control
              1. 13.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 13.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 13.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 13.2.1.4.6.13.2 Flow Control Trigger
              3. 13.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 13.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 13.2.1.4.6.15 Ethernet Switch Latency
            16. 13.2.1.4.6.16 MAC Emulation Control
            17. 13.2.1.4.6.17 MAC Command IDLE
            18. 13.2.1.4.6.18 CPSW Network Statistics
              1. 13.2.1.4.6.18.1 Rx-only Statistics Descriptions
                1. 13.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h)
                2. 13.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 13.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 13.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 13.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 13.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 13.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 13.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 13.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 13.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h)
                11. 13.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A05Ch)
                12. 13.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h)
                13. 13.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 13.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h)
                15. 13.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 13.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h)
                17. 13.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 13.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 13.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.1.4.6.18.1.19.11 ALE Policer Match (Offset = 3A0C0h)
                  12. 2.1.4.6.18.1.19.12 ALE Policer Match Red (Offset = 3A0C4h)
                  13. 2.1.4.6.18.1.19.13 ALE Policer Match Yellow (Offset = 3A0C8h)
              2. 13.2.1.4.6.18.2 Tx-only Statistics Descriptions
                1. 13.2.1.4.6.18.2.1  Good Tx Frames (Offset = 3A034h)
                2. 13.2.1.4.6.18.2.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 13.2.1.4.6.18.2.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 13.2.1.4.6.18.2.4  Pause Tx Frames (Offset = 3A040h)
                5. 13.2.1.4.6.18.2.5  Deferred Tx Frames (Offset = 3A044h)
                6. 13.2.1.4.6.18.2.6  Collisions (Offset = 3A048h)
                7. 13.2.1.4.6.18.2.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 13.2.1.4.6.18.2.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 13.2.1.4.6.18.2.9  Excessive Collisions (Offset = 3A054h)
                10. 13.2.1.4.6.18.2.10 Late Collisions (Offset = 3A058h)
                11. 13.2.1.4.6.18.2.11 Carrier Sense Errors (Offset = 3A060h)
                12. 13.2.1.4.6.18.2.12 Tx Octets (Offset = 3A064h)
                13. 13.2.1.4.6.18.2.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 13.2.1.4.6.18.2.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8)
                15. 13.2.1.4.6.18.2.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 13.2.1.4.6.18.2.16 Tx CRC Errors
              3. 13.2.1.4.6.18.3 Rx- and Tx (Shared) Statistics Descriptions
                1. 13.2.1.4.6.18.3.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 13.2.1.4.6.18.3.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 13.2.1.4.6.18.3.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 13.2.1.4.6.18.3.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 13.2.1.4.6.18.3.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 13.2.1.4.6.18.3.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 13.2.1.4.6.18.3.7 Net Octets (Offset = 3A080h)
              4. 13.2.1.4.6.18.4 1786
          7. 13.2.1.4.7  Common Platform Time Sync (CPTS)
            1. 13.2.1.4.7.1  CPTS Architecture
            2. 13.2.1.4.7.2  CPTS Initialization
            3. 13.2.1.4.7.3  32-bit Time Stamp Value
            4. 13.2.1.4.7.4  64-bit Time Stamp Value
            5. 13.2.1.4.7.5  64-Bit Timestamp Nudge
            6. 13.2.1.4.7.6  64-bit Timestamp PPM
            7. 13.2.1.4.7.7  Event FIFO
            8. 13.2.1.4.7.8  Timestamp Compare Output
              1. 13.2.1.4.7.8.1 Non-Toggle Mode: 32-bit
              2. 13.2.1.4.7.8.2 Non-Toggle Mode: 64-bit
              3. 13.2.1.4.7.8.3 Toggle Mode: 32-bit
              4. 13.2.1.4.7.8.4 Toggle Mode: 64-bit
            9. 13.2.1.4.7.9  Timestamp Sync Output
            10. 13.2.1.4.7.10 Timestamp GENFn Output
              1. 13.2.1.4.7.10.1 GENFn Nudge
              2. 13.2.1.4.7.10.2 GENFn PPM
            11. 13.2.1.4.7.11 Timestamp ESTFn
            12. 13.2.1.4.7.12 Time Sync Events
              1. 13.2.1.4.7.12.1 Time Stamp Push Event
              2. 13.2.1.4.7.12.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 13.2.1.4.7.12.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 13.2.1.4.7.12.4 Hardware Time Stamp Push Event
              5. 13.2.1.4.7.12.5 Ethernet Port Events
                1. 13.2.1.4.7.12.5.1 Ethernet Port Receive Event
                2. 13.2.1.4.7.12.5.2 Ethernet Port Transmit Event
                3. 13.2.1.4.7.12.5.3 1813
            13. 13.2.1.4.7.13 Timestamp Compare Event
              1. 13.2.1.4.7.13.1 32-Bit Mode
              2. 13.2.1.4.7.13.2 64-Bit Mode
            14. 13.2.1.4.7.14 Host Transmit Event
            15. 13.2.1.4.7.15 CPTS Interrupt Handling
          8. 13.2.1.4.8  CPDMA Host Interface
            1. 13.2.1.4.8.1 Functional Operation
            2. 13.2.1.4.8.2 Transmit CPDMA Interface
              1. 13.2.1.4.8.2.1 Transmit CPDMA Host Configuration
              2. 13.2.1.4.8.2.2 Transmit CPDMA Buffer Descriptors
              3. 13.2.1.4.8.2.3 Transmit Channel Teardown
            3. 13.2.1.4.8.3 Receive CPDMA Interface
              1. 13.2.1.4.8.3.1 Receive CPDMA Host Configuration
              2. 13.2.1.4.8.3.2 Receive DMA Host Configuration
              3. 13.2.1.4.8.3.3 Receive Channel Teardown
              4. 13.2.1.4.8.3.4 Receive CPDMA Hardware Controlled Packet Transmission
            4. 13.2.1.4.8.4 VLAN Aware Mode
            5. 13.2.1.4.8.5 VLAN Unaware Mode
            6. 13.2.1.4.8.6 CPDMA Big Endian Mode
            7. 13.2.1.4.8.7 CPDMA Command IDLE
            8. 13.2.1.4.8.8 CPDMA CPPI 3.0 Interface Bandwidth
          9. 13.2.1.4.9  CPPI Checksum Offload
            1. 13.2.1.4.9.1 CPPI Transmit Checksum Offload
              1. 13.2.1.4.9.1.1 IPV4 UDP
              2. 13.2.1.4.9.1.2 IPV4 TCP
              3. 13.2.1.4.9.1.3 IPV6 UDP
              4. 13.2.1.4.9.1.4 IPV6 TCP
              5. 13.2.1.4.9.1.5 Transmit Checksum Encapsulation Word
            2. 13.2.1.4.9.2 CPPI Receive Checksum Offload
              1. 13.2.1.4.9.2.1 Receive Checksum Encapsulation Word
          10. 13.2.1.4.10 Egress Packet Operations
          11. 13.2.1.4.11 MII Management Interface (MDIO)
            1. 13.2.1.4.11.1 MDIO Frame Formats
            2. 13.2.1.4.11.2 MDIO Functional Description
        5. 13.2.1.5 CPSW0 Programming Guide
          1. 13.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 13.2.1.5.2 Transmit Operation
          3. 13.2.1.5.3 Receive Operation
          4. 13.2.1.5.4 CPSW Reset
          5. 13.2.1.5.5 MDIO Software Interface
            1. 13.2.1.5.5.1 Initializing the MDIO Module
            2. 13.2.1.5.5.2 Writing Data To a PHY Register
            3. 13.2.1.5.5.3 Reading Data From a PHY Register
    3. 13.3 Memory Interfaces
      1. 13.3.1 Multimedia Card (MMC)
        1. 13.3.1.1 Introduction
          1. 13.3.1.1.1 MMCSD Features
          2. 13.3.1.1.2 Unsupported MMCSD Features
        2. 13.3.1.2 Integration
          1. 13.3.1.2.1 MMCSD Integration
          2. 13.3.1.2.2 MMCSD Connectivity Attributes
          3. 13.3.1.2.3 MMCSD Clock and Reset Management
          4. 13.3.1.2.4 MMCSD Pin List
        3. 13.3.1.3 Functional Description
          1. 13.3.1.3.1  MMC/SD/SDIO Functional Modes
            1. 13.3.1.3.1.1 MMC/SD/SDIO Connected to an MMC, an SD Card, or an SDIO Card
            2. 13.3.1.3.1.2 Protocol and Data Format
              1. 13.3.1.3.1.2.1 Protocol
              2. 13.3.1.3.1.2.2 Data Format
          2. 13.3.1.3.2  Resets
            1. 13.3.1.3.2.1 Hardware Reset
            2. 13.3.1.3.2.2 Software Reset
          3. 13.3.1.3.3  Power Management
            1. 13.3.1.3.3.1 Normal Mode
            2. 13.3.1.3.3.2 Idle Mode
            3. 13.3.1.3.3.3 Transition from Normal Mode to Smart-Idle Mode
            4. 13.3.1.3.3.4 Transition from Smart-Idle Mode to Normal Mode
            5. 13.3.1.3.3.5 Force-Idle Mode
            6. 13.3.1.3.3.6 Local Power Management
          4. 13.3.1.3.4  Interrupt Requests
            1. 13.3.1.3.4.1 Interrupt-Driven Operation
            2. 13.3.1.3.4.2 Polling
          5. 13.3.1.3.5  DMA Modes
            1. 13.3.1.3.5.1 DMA Responder Mode Operations
              1. 13.3.1.3.5.1.1 DMA Receive Mode
              2. 13.3.1.3.5.1.2 DMA Transmit Mode
          6. 13.3.1.3.6  Mode Selection
          7. 13.3.1.3.7  Buffer Management
            1. 13.3.1.3.7.1 Data Buffer
              1. 13.3.1.3.7.1.1 Memory Size, Block Length, and Buffer Management Relationship
              2. 13.3.1.3.7.1.2 Data Buffer Status
          8. 13.3.1.3.8  Transfer Process
            1. 13.3.1.3.8.1 Different Types of Commands
            2. 13.3.1.3.8.2 Different Types of Responses
          9. 13.3.1.3.9  Transfer or Command Status and Error Reporting
            1. 13.3.1.3.9.1 Busy Timeout for R1b, R5b Response Type
            2. 13.3.1.3.9.2 Busy Timeout After Write CRC Status
            3. 13.3.1.3.9.3 Write CRC Status Timeout
            4. 13.3.1.3.9.4 Read Data Timeout
          10. 13.3.1.3.10 Transfer Stop
          11. 13.3.1.3.11 Output Signals Generation
            1. 13.3.1.3.11.1 Generation on Falling Edge of MMC Clock
            2. 13.3.1.3.11.2 Generation on Rising Edge of MMC Clock
          12. 13.3.1.3.12 CE-ATA Command Completion Disable Management
          13. 13.3.1.3.13 Test Registers
          14. 13.3.1.3.14 MMC/SD/SDIO Hardware Status Features
        4. 13.3.1.4 Low-Level Programming Models
          1. 13.3.1.4.1 Surrounding Modules Global Initialization
          2. 13.3.1.4.2 MMC/SD/SDIO Controller Initialization Flow
            1. 13.3.1.4.2.1 Enable OCP and CLKADPI Clocks
            2. 13.3.1.4.2.2 SD Soft Reset Flow
            3. 13.3.1.4.2.3 Set SD Default Capabilities
            4. 13.3.1.4.2.4 Wake-Up Configuration
            5. 13.3.1.4.2.5 MMC Host and Bus Configuration
          3. 13.3.1.4.3 Operational Modes Configuration
            1. 13.3.1.4.3.1 Basic Operations for MMC/SD/SDIO Host Controller
            2. 13.3.1.4.3.2 Card Detection, Identification, and Selection
      2. 13.3.2 OptiFlash Submodules
        1. 13.3.2.1 RL2_OF
          1. 13.3.2.1.1 RL2_OF Overview
          2. 13.3.2.1.2 Remote L2 (RL2)
            1. 13.3.2.1.2.1 RL2 Overview
            2. 13.3.2.1.2.2 RL2 Supported Features
            3. 13.3.2.1.2.3 Tightly Coupled RL2 Tag Memory
            4. 13.3.2.1.2.4 Remote Cache Data Storage Memory
            5. 13.3.2.1.2.5 RL2 Cache Allocation
            6. 13.3.2.1.2.6 RL2 Statistics
            7. 13.3.2.1.2.7 Dual Mode
            8. 13.3.2.1.2.8 Critical Word First (CWF)
          3. 13.3.2.1.3 Fast Local Copy (FLC)
            1. 13.3.2.1.3.1 FLC Overview
              1. 13.3.2.1.3.1.1 FLC Supported Features
          4. 13.3.2.1.4 Region based Address Translation (RAT)
            1. 13.3.2.1.4.1 RAT Overview
              1. 13.3.2.1.4.1.1 RAT Supported Features
          5. 13.3.2.1.5 RL2_OF Interrupts and Error Handling
          6. 13.3.2.1.6 Emulation Debug
          7. 13.3.2.1.7 RL2_OF Safety Implementation
        2. 13.3.2.2 Flash Subsystem (FSS)
          1. 13.3.2.2.1 FSS Overview
            1. 13.3.2.2.1.1 FSS Features
            2. 13.3.2.2.1.2 FSS Not Supported Features
          2. 13.3.2.2.2 FSS Integration
            1. 13.3.2.2.2.1 FSS Integration
          3. 13.3.2.2.3 FSS Functional Description
            1. 13.3.2.2.3.1 FSS Detailed Block Diagram
            2. 13.3.2.2.3.2 FSS Memory Regions
              1. 13.3.2.2.3.2.1 FSS Boot Region and Selection
              2. 13.3.2.2.3.2.2 FSS Safety and Security
              3. 13.3.2.2.3.2.3 Read Optimizations
              4. 13.3.2.2.3.2.4 FSS XIP Prefetcher
              5. 13.3.2.2.3.2.5 Considerations for OSPI INDAC Read Mode with Address Translation
          4. 13.3.2.2.4 FSS Programming Guide
            1. 13.3.2.2.4.1 FSS Initialization Sequence
            2. 13.3.2.2.4.2 Real-time operating requirements
          5. 13.3.2.2.5 Octal Serial Peripheral Interface (OSPI)
            1. 13.3.2.2.5.1 OSPI Overview
              1. 13.3.2.2.5.1.1 OSPI Features
              2. 13.3.2.2.5.1.2 OSPI Not Supported Features
            2. 13.3.2.2.5.2 OSPI Environment
            3. 13.3.2.2.5.3 OSPI Integration
              1. 13.3.2.2.5.3.1 OSPI Integration
            4. 13.3.2.2.5.4 OSPI Functional Description
              1. 13.3.2.2.5.4.1  OSPI Block Diagram
                1. 13.3.2.2.5.4.1.1 Data Target Interface
                2. 13.3.2.2.5.4.1.2 Configuration Target Interface
                3. 13.3.2.2.5.4.1.3 OSPI Clock Domains
              2. 13.3.2.2.5.4.2  OSPI Modes
                1. 13.3.2.2.5.4.2.1 Read Data Capture
                  1. 3.2.2.5.4.2.1.1 Mechanisms of Data Capturing
                  2. 3.2.2.5.4.2.1.2 Data Capturing Mechanism Using Taps
                  3. 3.2.2.5.4.2.1.3 Data Capturing Mechanism Using PHY Module
                  4. 3.2.2.5.4.2.1.4 External Pull Down on DQS
              3. 13.3.2.2.5.4.3  OSPI Power Management
              4. 13.3.2.2.5.4.4  Auto HW Polling
              5. 13.3.2.2.5.4.5  Flash Reset
              6. 13.3.2.2.5.4.6  OSPI Memory Regions
              7. 13.3.2.2.5.4.7  OSPI Interrupt Requests
              8. 13.3.2.2.5.4.8  OSPI Data Interface
                1. 13.3.2.2.5.4.8.1 Data Interface Address Remapping
                2. 13.3.2.2.5.4.8.2 Write Protection
                3. 13.3.2.2.5.4.8.3 Access Forwarding
              9. 13.3.2.2.5.4.9  OSPI Direct Access Controller (DAC)
              10. 13.3.2.2.5.4.10 OSPI Indirect Access Controller (INDAC)
                1. 13.3.2.2.5.4.10.1 Indirect Read Controller
                  1. 3.2.2.5.4.10.1.1 Indirect Read Transfer Process
                2. 13.3.2.2.5.4.10.2 Indirect Write Controller
                  1. 3.2.2.5.4.10.2.1 Indirect Write Transfer Process
                3. 13.3.2.2.5.4.10.3 Indirect Access Queuing
                4. 13.3.2.2.5.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
                5. 13.3.2.2.5.4.10.5 Accessing the SRAM
              11. 13.3.2.2.5.4.11 OSPI Software-Triggered Instruction Generator (STIG)
                1. 13.3.2.2.5.4.11.1 Servicing a STIG Request
              12. 13.3.2.2.5.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
              13. 13.3.2.2.5.4.13 OSPI Command Translation
              14. 13.3.2.2.5.4.14 Selecting the Flash Instruction Type
              15. 13.3.2.2.5.4.15 OSPI Data Integrity
              16. 13.3.2.2.5.4.16 OSPI PHY Module
                1. 13.3.2.2.5.4.16.1 PHY Pipeline Mode
                2. 13.3.2.2.5.4.16.2 Read Data Capturing by the PHY Module
            5. 13.3.2.2.5.5 OSPI Programming Guide
              1. 13.3.2.2.5.5.1 Configuring the OSPI Controller for Use After Reset
              2. 13.3.2.2.5.5.2 Configuring the OSPI Controller for Optimal Use
              3. 13.3.2.2.5.5.3 Using the Flash Command Control Register (STIG Operation)
          6. 13.3.2.2.6 Firmware Upgrade Over the Air (FOTA) Accelerator
            1. 13.3.2.2.6.1 FOTA Overview
            2. 13.3.2.2.6.2 FOTA High Level Sequence
            3. 13.3.2.2.6.3 Programming Considerations for FOTA
          7. 13.3.2.2.7 On the Fly Encryption and Authentication (OTFA)
            1. 13.3.2.2.7.1 OTFA Overview
              1. 13.3.2.2.7.1.1 Features Supported
              2. 13.3.2.2.7.1.2 Features Not Supported
            2. 13.3.2.2.7.2 OTFA Functional Description
              1. 13.3.2.2.7.2.1 Authentication Operations
              2. 13.3.2.2.7.2.2 AES Operations
              3. 13.3.2.2.7.2.3 Modes of Operation
                1. 13.3.2.2.7.2.3.1 GCM (Encryption + Authentication generation )
                2. 13.3.2.2.7.2.3.2 GCM (Decryption + Authentication verification )
                3. 13.3.2.2.7.2.3.3 GMAC (Authentication generation only )
                4. 13.3.2.2.7.2.3.4 GMAC (Authentication verification only )
            3. 13.3.2.2.7.3 OTFA Programming Model
          8. 13.3.2.2.8 Error Correction Code (ECC) and Safety
            1. 13.3.2.2.8.1 ECC Overview
              1. 13.3.2.2.8.1.1 Features Supported
              2. 13.3.2.2.8.1.2 ECCM Address Translation
            2. 13.3.2.2.8.2 ECCM Calculation
            3. 13.3.2.2.8.3 Modes of Operation
              1. 13.3.2.2.8.3.1 RD Modes
              2. 13.3.2.2.8.3.2 WR Modes
            4. 13.3.2.2.8.4 Read Operations
            5. 13.3.2.2.8.5 Memory Address Translation
            6. 13.3.2.2.8.6 ECCM Error Reporting
    4. 13.4 Industrial and Control Interfaces
      1. 13.4.1 Modular Controller Area Network (MCAN)
        1. 13.4.1.1 MCAN Overview
          1. 13.4.1.1.1 MCAN Features
          2. 13.4.1.1.2 MCAN Not Supported Features
        2. 13.4.1.2 MCAN Environment
          1. 13.4.1.2.1 CAN Network Basics
        3. 13.4.1.3 MCAN Integration
        4. 13.4.1.4 MCAN Functional Description
          1. 13.4.1.4.1  Module Clocking Requirements
          2. 13.4.1.4.2  Interrupt and DMA Requests
            1. 13.4.1.4.2.1 Interrupt Requests
            2. 13.4.1.4.2.2 DMA Requests
          3. 13.4.1.4.3  Operating Modes
            1. 13.4.1.4.3.1 Software Initialization
            2. 13.4.1.4.3.2 Normal Operation
            3. 13.4.1.4.3.3 CAN FD Operation
            4. 13.4.1.4.3.4 Transmitter Delay Compensation
              1. 13.4.1.4.3.4.1 Description
              2. 13.4.1.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 13.4.1.4.3.5 Restricted Operation Mode
            6. 13.4.1.4.3.6 Bus Monitoring Mode
            7. 13.4.1.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 13.4.1.4.3.7.1 Frame Transmission in DAR Mode
            8. 13.4.1.4.3.8 Power Down (Sleep Mode)
              1. 13.4.1.4.3.8.1 External Clock Stop Mode
              2. 13.4.1.4.3.8.2 Suspend Mode
              3. 13.4.1.4.3.8.3 Wakeup request
            9. 13.4.1.4.3.9 Test Modes
              1. 13.4.1.4.3.9.1 Internal Loopback Mode
          4. 13.4.1.4.4  Timestamp Generation
            1. 13.4.1.4.4.1 External Timestamp Counter
          5. 13.4.1.4.5  Timeout Counter
          6. 13.4.1.4.6  ECC Support
            1. 13.4.1.4.6.1 ECC Wrapper
          7. 13.4.1.4.7  Rx Handling
            1. 13.4.1.4.7.1 Acceptance Filtering
              1. 13.4.1.4.7.1.1 Range Filter
              2. 13.4.1.4.7.1.2 Filter for specific IDs
              3. 13.4.1.4.7.1.3 Classic Bit Mask Filter
              4. 13.4.1.4.7.1.4 Standard Message ID Filtering
              5. 13.4.1.4.7.1.5 Extended Message ID Filtering
            2. 13.4.1.4.7.2 Rx FIFOs
              1. 13.4.1.4.7.2.1 Rx FIFO Blocking Mode
              2. 13.4.1.4.7.2.2 Rx FIFO Overwrite Mode
            3. 13.4.1.4.7.3 Dedicated Rx Buffers
              1. 13.4.1.4.7.3.1 Rx Buffer Handling
            4. 13.4.1.4.7.4 Debug on CAN Support
          8. 13.4.1.4.8  Tx Handling
            1. 13.4.1.4.8.1 Transmit Pause
            2. 13.4.1.4.8.2 Dedicated Tx Buffers
            3. 13.4.1.4.8.3 Tx FIFO
            4. 13.4.1.4.8.4 Tx Queue
            5. 13.4.1.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 13.4.1.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 13.4.1.4.8.7 Transmit Cancellation
            8. 13.4.1.4.8.8 Tx Event Handling
          9. 13.4.1.4.9  FIFO Acknowledge Handling
          10. 13.4.1.4.10 Message RAM
            1. 13.4.1.4.10.1 Message RAM Configuration
            2. 13.4.1.4.10.2 Rx Buffer and FIFO Element
            3. 13.4.1.4.10.3 Tx Buffer Element
            4. 13.4.1.4.10.4 Tx Event FIFO Element
            5. 13.4.1.4.10.5 Standard Message ID Filter Element
            6. 13.4.1.4.10.6 Extended Message ID Filter Element
        5. 13.4.1.5 MCAN Programming Guide
      2. 13.4.2 Local Interconnect Network (LIN)
        1. 13.4.2.1 LIN Overview
          1. 13.4.2.1.1 SCI Mode Features
          2. 13.4.2.1.2 LIN Mode Features
          3. 13.4.2.1.3 Block Diagram
        2. 13.4.2.2 LIN Integration
        3. 13.4.2.3 Serial Communications Interface Module
          1. 13.4.2.3.1 SCI Communication Formats
            1. 13.4.2.3.1.1 SCI Frame Formats
            2. 13.4.2.3.1.2 SCI Asynchronous Timing Mode
            3. 13.4.2.3.1.3 SCI Baud Rate
            4. 13.4.2.3.1.4 SCI Multiprocessor Communication Modes
              1. 13.4.2.3.1.4.1 Idle-Line Multiprocessor Modes
              2. 13.4.2.3.1.4.2 Address-Bit Multiprocessor Mode
            5. 13.4.2.3.1.5 SCI Multibuffered Mode
          2. 13.4.2.3.2 SCI Interrupts
            1. 13.4.2.3.2.1 Transmit Interrupt
            2. 13.4.2.3.2.2 Receive Interrupt
            3. 13.4.2.3.2.3 WakeUp Interrupt
            4. 13.4.2.3.2.4 Error Interrupts
          3. 13.4.2.3.3 SCI DMA Interface
            1. 13.4.2.3.3.1 Receive DMA Requests
            2. 13.4.2.3.3.2 Transmit DMA Requests
          4. 13.4.2.3.4 SCI Configurations
            1. 13.4.2.3.4.1 Receiving Data
              1. 13.4.2.3.4.1.1 Receiving Data in Single-Buffer Mode
              2. 13.4.2.3.4.1.2 Receiving Data in Multibuffer Mode
            2. 13.4.2.3.4.2 Transmitting Data
              1. 13.4.2.3.4.2.1 Transmitting Data in Single-Buffer Mode
              2. 13.4.2.3.4.2.2 Transmitting Data in Multibuffer Mode
          5. 13.4.2.3.5 SCI Low-Power Mode
            1. 13.4.2.3.5.1 Sleep Mode for Multiprocessor Communication
        4. 13.4.2.4 Local Interconnect Network Module
          1. 13.4.2.4.1 LIN Communication Formats
            1. 13.4.2.4.1.1  LIN Standards
            2. 13.4.2.4.1.2  Message Frame
              1. 13.4.2.4.1.2.1 Message Header
              2. 13.4.2.4.1.2.2 Response
            3. 13.4.2.4.1.3  Synchronizer
            4. 13.4.2.4.1.4  Baud Rate
              1. 13.4.2.4.1.4.1 Fractional Divider
              2. 13.4.2.4.1.4.2 Superfractional Divider
                1. 13.4.2.4.1.4.2.1 Superfractional Divider In LIN Mode
            5. 13.4.2.4.1.5  Header Generation
              1. 13.4.2.4.1.5.1 Event Triggered Frame Handling
              2. 13.4.2.4.1.5.2 Header Reception and Adaptive Baud Rate
            6. 13.4.2.4.1.6  Extended Frames Handling
            7. 13.4.2.4.1.7  Timeout Control
              1. 13.4.2.4.1.7.1 No-Response Error (NRE)
              2. 13.4.2.4.1.7.2 Bus Idle Detection
              3. 13.4.2.4.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
            8. 13.4.2.4.1.8  TXRX Error Detector (TED)
              1. 13.4.2.4.1.8.1 Bit Errors
              2. 13.4.2.4.1.8.2 Physical Bus Errors
              3. 13.4.2.4.1.8.3 ID Parity Errors
              4. 13.4.2.4.1.8.4 Checksum Errors
            9. 13.4.2.4.1.9  Message Filtering and Validation
            10. 13.4.2.4.1.10 Receive Buffers
            11. 13.4.2.4.1.11 Transmit Buffers
          2. 13.4.2.4.2 LIN Interrupts
          3. 13.4.2.4.3 Servicing LIN Interrupts
          4. 13.4.2.4.4 LIN Configurations
            1. 13.4.2.4.4.1 Receiving Data
              1. 13.4.2.4.4.1.1 Receiving Data in Single-Buffer Mode
              2. 13.4.2.4.4.1.2 Receiving Data in Multibuffer Mode
            2. 13.4.2.4.4.2 Transmitting Data
              1. 13.4.2.4.4.2.1 Transmitting Data in Single-Buffer Mode
              2. 13.4.2.4.4.2.2 Transmitting Data in Multibuffer Mode
        5. 13.4.2.5 Low-Power Mode
          1. 13.4.2.5.1 Entering Sleep Mode
          2. 13.4.2.5.2 Wakeup
          3. 13.4.2.5.3 Wakeup Timeouts
        6. 13.4.2.6 Emulation Mode
        7. 13.4.2.7 LIN Programming Guide
    5. 13.5 Timer Modules
      1. 13.5.1 Real Time Interrupts/Windowed Watchdog Timer (RTI/WWDT)
        1. 13.5.1.1 RTI/WWDT Overview
          1. 13.5.1.1.1 RTI Features
          2. 13.5.1.1.2 RTI Unsupported Features
        2. 13.5.1.2 RTI Integration
        3. 13.5.1.3 WWDT Integration
        4. 13.5.1.4 RTI Functional Description
          1. 13.5.1.4.1 RTI Digital Windowed Watchdog
            1. 13.5.1.4.1.1 RTI Debug Mode Behavior
          2. 13.5.1.4.2 RTI Digital Watchdog
          3. 13.5.1.4.3 RTI Counter Operation
        5. 13.5.1.5 RTI/WWDT Programming Guide
    6. 13.6 Internal Diagnostics Modules
      1. 13.6.1 Dual Clock Comparator (DCC)
        1. 13.6.1.1 DCC Overview
          1. 13.6.1.1.1 DCC Features
          2. 13.6.1.1.2 DCC Not Supported Features
        2. 13.6.1.2 DCC Integration
          1. 13.6.1.2.1 DCC Integration
        3. 13.6.1.3 DCC Functional Description
          1. 13.6.1.3.1 DCC Counter Operation
          2. 13.6.1.3.2 DCC Clock Sources
          3. 13.6.1.3.3 DCC Mode of Operation
            1. 13.6.1.3.3.1 DCC Single-Shot Mode
            2. 13.6.1.3.3.2 DCC Continuous Mode
              1. 13.6.1.3.3.2.1 DCC Continue on Error
              2. 13.6.1.3.3.2.2 DCC Error Count
          4. 13.6.1.3.4 DCC Error Trajectory Record
            1. 13.6.1.3.4.1 DCC FIFO Capturing for Errors
            2. 13.6.1.3.4.2 DCC FIFO in Continuous Capture Mode
            3. 13.6.1.3.4.3 DCC FIFO Details
          5. 13.6.1.3.5 DCC Count Read Registers
          6. 13.6.1.3.6 Limp Mode Generation
      2. 13.6.2 ECC Aggregator
        1. 13.6.2.1 ECC Aggregator Overview
          1. 13.6.2.1.1 Memory Protection System using ECC
          2. 13.6.2.1.2 ECC Aggregator Features
        2. 13.6.2.2 ECC Aggregator Integration
          1. 13.6.2.2.1 ECC Aggregator Integration
        3. 13.6.2.3 ECC Aggregator Functional Description
          1. 13.6.2.3.1 ECC Aggregator Block Diagram
          2. 13.6.2.3.2 ECC Aggregator Register Groups
          3. 13.6.2.3.3 Read Access to the ECC Control and Status Registers
          4. 13.6.2.3.4 Serial Write Operation
          5. 13.6.2.3.5 Interrupts
          6. 13.6.2.3.6 Inject Only Mode
      3. 13.6.3 Error Signaling Module (ESM)
        1. 13.6.3.1 ESM Overview
        2. 13.6.3.2 ESM Features
        3. 13.6.3.3 ESM Integration
        4. 13.6.3.4 ESM Functional Description
          1. 13.6.3.4.1  ESM Functional Operation
          2. 13.6.3.4.2  Error Event Inputs
          3. 13.6.3.4.3  Error Interrupt Outputs
          4. 13.6.3.4.4  ESM Error Pin Output
          5. 13.6.3.4.5  Error Pin Behavior During Reset
          6. 13.6.3.4.6  PWM Mode
          7. 13.6.3.4.7  Minimum Time Interval
          8. 13.6.3.4.8  Safety Protection for MMRs
          9. 13.6.3.4.9  ESM Interrupts
          10. 13.6.3.4.10 Programming Guide
            1. 13.6.3.4.10.1 Configuration Error Interrupt
            2. 13.6.3.4.10.2 Low Priority Error Interrupt
              1. 13.6.3.4.10.2.1 Level Event
              2. 13.6.3.4.10.2.2 Pulse Event
            3. 13.6.3.4.10.3 High Priority Error Interrupt
              1. 13.6.3.4.10.3.1 Level Event
              2. 13.6.3.4.10.3.2 Pulse Event
            4. 13.6.3.4.10.4 Critical Priority Error Interrupt
              1. 13.6.3.4.10.4.1 Level Event
      4. 13.6.4 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 13.6.4.1 MCRC Overview
          1. 13.6.4.1.1 MCRC Features
        2. 13.6.4.2 MCRC Integration
        3. 13.6.4.3 MCRC Functional Description
          1. 13.6.4.3.1  MCRC Block Diagram
          2. 13.6.4.3.2  MCRC General Operation
          3. 13.6.4.3.3  MCRC Modes of Operation
            1. 13.6.4.3.3.1 AUTO Mode
            2. 13.6.4.3.3.2 Semi-CPU Mode
            3. 13.6.4.3.3.3 Full-CPU Mode
          4. 13.6.4.3.4  PSA Signature Register
          5. 13.6.4.3.5  PSA Sector Signature Register
          6. 13.6.4.3.6  CRC Value Register
          7. 13.6.4.3.7  Raw Data Register
          8. 13.6.4.3.8  Example DMA Controller Setup
            1. 13.6.4.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 13.6.4.3.8.2 AUTO Mode Using Software Trigger
            3. 13.6.4.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 13.6.4.3.9  Pattern Count Register
          10. 13.6.4.3.10 Sector Count Register/Current Sector Register
          11. 13.6.4.3.11 Interrupts
            1. 13.6.4.3.11.1 Overrun Interrupt
            2. 13.6.4.3.11.2 Timeout Interrupt
            3. 13.6.4.3.11.3 Underrun Interrupt
            4. 13.6.4.3.11.4 Compression Complete Interrupt
            5. 13.6.4.3.11.5 Interrupt Offset Register
            6. 13.6.4.3.11.6 Error Handling
          12. 13.6.4.3.12 Power Down Mode
          13. 13.6.4.3.13 Emulation
        4. 13.6.4.4 MCRC Programming Examples
          1. 13.6.4.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 13.6.4.4.1.1 DMA Setup
            2. 13.6.4.4.1.2 Timer Setup
            3. 13.6.4.4.1.3 CRC Setup
          2. 13.6.4.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 13.6.4.4.2.1 DMA Setup
            2. 13.6.4.4.2.2 CRC Setup
          3. 13.6.4.4.3 Example: Semi-CPU Mode
            1. 13.6.4.4.3.1 DMA Setup
            2. 13.6.4.4.3.2 Timer Setup
            3. 13.6.4.4.3.3 CRC Setup
          4. 13.6.4.4.4 Example: Full-CPU Mode
            1. 13.6.4.4.4.1 CRC Setup
      5. 13.6.5 Self-Test Controller (STC)
        1. 13.6.5.1 STC Overview
          1. 13.6.5.1.1 Unsupported Features
          2. 13.6.5.1.2 STC Memory Map
          3. 13.6.5.1.3 OPMISR Concept
        2. 13.6.5.2 Block Diagram
        3. 13.6.5.3 Module Description
          1. 13.6.5.3.1 ROM Interface
          2. 13.6.5.3.2 FSM and Sequence Control
            1. 13.6.5.3.2.1 Clock Control
            2. 13.6.5.3.2.2 MISR Compare Block
          3. 13.6.5.3.3 Register Block
          4. 13.6.5.3.4 VBUSP Interface
          5. 13.6.5.3.5 STC Flow
          6. 13.6.5.3.6 Programming Sequence
          7. 13.6.5.3.7 ROM Organization
            1. 13.6.5.3.7.1 TR_T: Transition Delay Methodology Type
            2. 13.6.5.3.7.2 FT: Fault Model for the BIST Run
            3. 13.6.5.3.7.3 SEG_ID[1:0]
            4. 13.6.5.3.7.4 Pattern Count ( patt_count[9:0] )
            5. 13.6.5.3.7.5 MISR_GOLDEN[895:0]: Golden Signature Data Bits
            6. 13.6.5.3.7.6 LP_MISR_GOLDEN[895:0]: Low Power Mode Golden Signature Data Bits
            7. 13.6.5.3.7.7 INV_MISR_GOLDEN[895:0]: Inverse Mode Golden Signature Data Bits
            8. 13.6.5.3.7.8 LP_INV_MISR_GOLDEN[895:0]: Low Power Inverse Mode Golden Signature Data Bits
            9. 13.6.5.3.7.9 Pn_SDm[7:0] (n - no. of patterns, m - scan chain length): OP-MISR Scan Data
      6. 13.6.6 Programmable Built-In Self-Test (PBIST) Module
        1. 13.6.6.1 Overview
          1. 13.6.6.1.1 Features of PBIST
          2. 13.6.6.1.2 PBIST vs. Application Software-Based Testing
          3. 13.6.6.1.3 PBIST Block Diagram
            1. 13.6.6.1.3.1 On-chip ROM
            2. 13.6.6.1.3.2 Host Processor Interface to the PBIST Controller Registers
            3. 13.6.6.1.3.3 Memory Data Path
        2. 13.6.6.2 PBIST Flow
        3. 13.6.6.3 PBIST RAM-ROM Memory and Algorithm Group Configuration
        4. 13.6.6.4 Memory Test Algorithms on the On-chip ROM
  16. 14On-Chip Debug
    1. 14.1 On-Chip Debug
      1. 14.1.1 On-Chip Debug Overview
      2. 14.1.2 On-Chip Debug Features
      3. 14.1.3 On-Chip Debug Functional Description
        1. 14.1.3.1 On-Chip Debug Block Diagram
        2. 14.1.3.2 Device Interfaces
          1. 14.1.3.2.1 JTAG Interface
          2. 14.1.3.2.2 Trace Port Interface
        3. 14.1.3.3 Debug and Boundary Scan Access and Control
          1. 14.1.3.3.1 DAP
            1. 14.1.3.3.1.1 Debug Subsystem Address Map
          2. 14.1.3.3.2 Boundary Scan
        4. 14.1.3.4 Reset Management
        5. 14.1.3.5 Debug Cross Triggering
          1. 14.1.3.5.1 R5F CTI Trigger Connections
          2. 14.1.3.5.2 Cortex M4 CTI Trigger Connections
          3. 14.1.3.5.3 STM CTI Trigger Connections
          4. 14.1.3.5.4 DEBUGSS CS-CTI Trigger Connections
        6. 14.1.3.6 SOC Debug and Trace
          1. 14.1.3.6.1 Software Messaging Trace
          2. 14.1.3.6.2 Debug Aware Peripherals
        7. 14.1.3.7 Trace Infrastructure
          1. 14.1.3.7.1 Trace Sources
          2. 14.1.3.7.2 Trace Distribution
          3. 14.1.3.7.3 Trace Sinks
    2. 14.2 Arm Debug Links
  17.   Revision History

10.4.2 R5FSS0_CORE1 Interrupt Map

Table 10-18 shows the mapping of events to the R5FSS0_CORE1.

Both R5FSS0_CORE1 and R5FSS0_CORE0 use the R5FSS0_CORE0 interrupt map when operating in lockstep mode.

Table 10-18 R5FSS0_CORE1 Interrupt Map
Interrupt Input Line Interrupt ID Source Interrupt Interrupt type
R5FSS0_CORE1_INTR_IN_0 0 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_0 Level
R5FSS0_CORE1_INTR_IN_1 1 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_1 Level
R5FSS0_CORE1_INTR_IN_2 2 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_2 Level
R5FSS0_CORE1_INTR_IN_3 3 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_3 Level
R5FSS0_CORE1_INTR_IN_4 4 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_4 Level
R5FSS0_CORE1_INTR_IN_5 5 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_5 Level
R5FSS0_CORE1_INTR_IN_6 6 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_6 Level
R5FSS0_CORE1_INTR_IN_7 7 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_HOST_INTR_PEND_7 Level
R5FSS0_CORE1_INTR_IN_8 8 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_RX_SOF_INTR_REQ_0 Pulse
R5FSS0_CORE1_INTR_IN_9 9 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_RX_SOF_INTR_REQ_1 Pulse
R5FSS0_CORE1_INTR_IN_10 10 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_TX_SOF_INTR_REQ_0 Pulse
R5FSS0_CORE1_INTR_IN_11 11 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_TX_SOF_INTR_REQ_1 Pulse
R5FSS0_CORE1_INTR_IN_12 12 R5FSS0_CORE1_INTR_CPSW0_FH_INTR

Pulse
R5FSS0_CORE1_INTR_IN_13 13 R5FSS0_CORE1_INTR_CPSW0_TH_INTR

Pulse
R5FSS0_CORE1_INTR_IN_14 14 R5FSS0_CORE1_INTR_CPSW0_TH_THRESH_INTR

Level
R5FSS0_CORE1_INTR_IN_15 15 R5FSS0_CORE1_INTR_CPSW0_MISC_INTR

Level
R5FSS0_CORE1_INTR_IN_16 16 R5FSS0_CORE1_INTR_LIN0_INTR_0

Pulse
R5FSS0_CORE1_INTR_IN_17 17 R5FSS0_CORE1_INTR_LIN0_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_18 18 R5FSS0_CORE1_INTR_LIN1_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_19 19 R5FSS0_CORE1_INTR_LIN1_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_20 20 R5FSS0_CORE1_INTR_LIN2_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_21 21 R5FSS0_CORE1_INTR_LIN2_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_22 22 R5FSS0_CORE1_INTR_LIN3_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_23 23 R5FSS0_CORE1_INTR_LIN3_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_24 24 R5FSS0_CORE1_INTR_LIN4_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_25 25 R5FSS0_CORE1_INTR_LIN4_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_26 26 R5FSS0_CORE1_INTR_MCAN0_EXT_TS_ROLLOVER_LVL_INT_0

Level
R5FSS0_CORE1_INTR_IN_27 27 R5FSS0_CORE1_INTR_MCAN0_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_28 28 R5FSS0_CORE1_INTR_MCAN0_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_29 29 R5FSS0_CORE1_INTR_MCAN1_EXT_TS_ROLLOVER_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_30 30 R5FSS0_CORE1_INTR_MCAN1_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_31 31 R5FSS0_CORE1_INTR_MCAN1_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_32 32 R5FSS0_CORE1_INTR_MCAN2_EXT_TS_ROLLOVER_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_33 33 R5FSS0_CORE1_INTR_MCAN2_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_34 34 R5FSS0_CORE1_INTR_MCAN2_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_35 35 R5FSS0_CORE1_INTR_MCAN3_EXT_TS_ROLLOVER_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_36 36 R5FSS0_CORE1_INTR_MCAN3_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_37 37 R5FSS0_CORE1_INTR_MCAN3_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_38 38 R5FSS0_CORE1_INTR_UART0_IRQ Level
R5FSS0_CORE1_INTR_IN_39 39 R5FSS0_CORE1_INTR_UART1_IRQ Level
R5FSS0_CORE1_INTR_IN_40 40 R5FSS0_CORE1_INTR_UART2_IRQ Level
R5FSS0_CORE1_INTR_IN_41 41 R5FSS0_CORE1_INTR_UART3_IRQ Level
R5FSS0_CORE1_INTR_IN_42 42 R5FSS0_CORE1_INTR_UART4_IRQ Level
R5FSS0_CORE1_INTR_IN_43 43 R5FSS0_CORE1_INTR_UART5_IRQ Level
R5FSS0_CORE1_INTR_IN_44 44 R5FSS0_CORE1_INTR_I2C0_IRQ

Pulse
R5FSS0_CORE1_INTR_IN_45 45 R5FSS0_CORE1_INTR_I2C1_IRQ

Pulse
R5FSS0_CORE1_INTR_IN_46 46 R5FSS0_CORE1_INTR_I2C2_IRQ

Pulse
R5FSS0_CORE1_INTR_IN_47 47 R5FSS0_CORE1_INTR_I2C3_IRQ

Pulse
R5FSS0_CORE1_INTR_IN_48 48 R5FSS0_CORE1_INTR_DTHE_SHA_S_INT

Level
R5FSS0_CORE1_INTR_IN_49 49 R5FSS0_CORE1_INTR_DTHE_SHA_P_INT

Level
R5FSS0_CORE1_INTR_IN_50 50 R5FSS0_CORE1_INTR_DTHE_TRNG_INT

Level
R5FSS0_CORE1_INTR_IN_51 51 R5FSS0_CORE1_INTR_DTHE_PKAE_INT

Level
R5FSS0_CORE1_INTR_IN_52 52 R5FSS0_CORE1_INTR_DTHE_AES_S_INT

Level
R5FSS0_CORE1_INTR_IN_53 53 R5FSS0_CORE1_INTR_DTHE_AES_P_INT

Level
R5FSS0_CORE1_INTR_IN_54 54 R5FSS0_CORE1_INTR_OSPI0_INT

Level
R5FSS0_CORE1_INTR_IN_55 55 R5FSS0_CORE1_INTR_TPCC_A_INTG

Pulse
R5FSS0_CORE1_INTR_IN_56 56 R5FSS0_CORE1_INTR_TPCC_A_INT_0 Pulse
R5FSS0_CORE1_INTR_IN_57 57 R5FSS0_CORE1_INTR_TPCC_A_INT_1 Pulse
R5FSS0_CORE1_INTR_IN_58 58 R5FSS0_CORE1_INTR_TPCC_A_INT_2 Pulse
R5FSS0_CORE1_INTR_IN_59 59 R5FSS0_CORE1_INTR_TPCC_A_INT_3 Pulse
R5FSS0_CORE1_INTR_IN_60 60 R5FSS0_CORE1_INTR_TPCC_A_INT_4 Pulse
R5FSS0_CORE1_INTR_IN_61 61 R5FSS0_CORE1_INTR_TPCC_A_INT_5 Pulse
R5FSS0_CORE1_INTR_IN_62 62 R5FSS0_CORE1_INTR_TPCC_A_INT_6 Pulse
R5FSS0_CORE1_INTR_IN_63 63 R5FSS0_CORE1_INTR_TPCC_A_INT_7 Pulse
R5FSS0_CORE1_INTR_IN_64 64 R5FSS0_CORE1_INTR_TPCC_A_ERRINT Pulse
R5FSS0_CORE1_INTR_IN_65 65 R5FSS0_CORE1_INTR_TPCC_A_MPINT Pulse
R5FSS0_CORE1_INTR_IN_66 66 R5FSS0_CORE1_INTR_TPTC0_ERINT_0 Pulse
R5FSS0_CORE1_INTR_IN_67 67 R5FSS0_CORE1_INTR_TPTC0_ERINT_1 Pulse
R5FSS0_CORE1_INTR_IN_68 68 R5FSS0_CORE1_INTR_MCRC0_INT Level
R5FSS0_CORE1_INTR_IN_69 69 R5FSS0_CORE1_INTR_MPU_ADDR_ERRAGG Level
R5FSS0_CORE1_INTR_IN_70 70 R5FSS0_CORE1_INTR_MPU_PROT_ERRAGG Level
R5FSS0_CORE1_INTR_IN_71 71 R5FSS0_CORE1_INTR_PBIST_DONE Level
R5FSS0_CORE1_INTR_IN_72 72 R5FSS0_CORE1_INTR_TPCC_A_INTAGGR Level
R5FSS0_CORE1_INTR_IN_73 73 R5FSS0_CORE1_INTR_TPCC_A_ERRAGGR Level
R5FSS0_CORE1_INTR_IN_74 74 R5FSS0_CORE1_INTR_DCC0_DONE Level
R5FSS0_CORE1_INTR_IN_75 75 R5FSS0_CORE1_INTR_DCC1_DONE Level
R5FSS0_CORE1_INTR_IN_76 76 R5FSS0_CORE1_INTR_DCC2_DONE Level
R5FSS0_CORE1_INTR_IN_77 77 R5FSS0_CORE1_INTR_DCC3_DONE Level
R5FSS0_CORE1_INTR_IN_78 78 R5FSS0_CORE1_INTR_MCSPI0_INTR Level
R5FSS0_CORE1_INTR_IN_79 79 R5FSS0_CORE1_INTR_MCSPI1_INTR Level
R5FSS0_CORE1_INTR_IN_80 80 R5FSS0_CORE1_INTR_MCSPI2_INTR Level
R5FSS0_CORE1_INTR_IN_81 81 R5FSS0_CORE1_INTR_MCSPI3_INTR Level
R5FSS0_CORE1_INTR_IN_82 82 R5FSS0_CORE1_INTR_MCSPI4_INTR Level
R5FSS0_CORE1_INTR_IN_83 83 R5FSS0_CORE1_INTR_MMC0_INTR Level
R5FSS0_CORE1_INTR_IN_84 84 R5FSS0_CORE1_INTR_RTI0_INTR_0

Pulse
R5FSS0_CORE1_INTR_IN_85 85 R5FSS0_CORE1_INTR_RTI0_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_86 86 R5FSS0_CORE1_INTR_RTI0_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_87 87 R5FSS0_CORE1_INTR_RTI0_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_88 88 R5FSS0_CORE1_INTR_RESERVED

NA
R5FSS0_CORE1_INTR_IN_89 89 R5FSS0_CORE1_INTR_RTI0_OVERFLOW_INT0 Pulse
R5FSS0_CORE1_INTR_IN_90 90 R5FSS0_CORE1_INTR_RTI0_OVERFLOW_INT1 Pulse
R5FSS0_CORE1_INTR_IN_91 91 R5FSS0_CORE1_INTR_RTI1_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_92 92 R5FSS0_CORE1_INTR_RTI1_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_93 93 R5FSS0_CORE1_INTR_RTI1_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_94 94 R5FSS0_CORE1_INTR_RTI1_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_95 95 R5FSS0_CORE1_INTR_RESERVED

NA
R5FSS0_CORE1_INTR_IN_96 96 R5FSS0_CORE1_INTR_RTI1_OVERFLOW_INT0 Pulse
R5FSS0_CORE1_INTR_IN_97 97 R5FSS0_CORE1_INTR_RTI1_OVERFLOW_INT1 Pulse
R5FSS0_CORE1_INTR_IN_98 98 R5FSS0_CORE1_INTR_RTI2_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_99 99 R5FSS0_CORE1_INTR_RTI2_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_100 100 R5FSS0_CORE1_INTR_RTI2_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_101 101 R5FSS0_CORE1_INTR_RTI2_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_102 102 R5FSS0_CORE1_INTR_RESERVED

NA
R5FSS0_CORE1_INTR_IN_103 103 R5FSS0_CORE1_INTR_RTI2_OVERFLOW_INT0 Pulse
R5FSS0_CORE1_INTR_IN_104 104 R5FSS0_CORE1_INTR_RTI2_OVERFLOW_INT1 Pulse
R5FSS0_CORE1_INTR_IN_105 105 R5FSS0_CORE1_INTR_RTI3_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_106 106 R5FSS0_CORE1_INTR_RTI3_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_107 107 R5FSS0_CORE1_INTR_RTI3_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_108 108 R5FSS0_CORE1_INTR_RTI3_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_109 109 R5FSS0_CORE1_INTR_RESERVED

NA
R5FSS0_CORE1_INTR_IN_110 110 R5FSS0_CORE1_INTR_RTI3_OVERFLOW_INT0 Pulse
R5FSS0_CORE1_INTR_IN_111 111 R5FSS0_CORE1_INTR_RTI3_OVERFLOW_INT1 Pulse
R5FSS0_CORE1_INTR_IN_112 112 R5FSS0_CORE1_INTR_RESERVED

NA
R5FSS0_CORE1_INTR_IN_113 113 R5FSS0_CORE1_INTR_ESM0_ESM_INT_CFG

Level
R5FSS0_CORE1_INTR_IN_114 114 R5FSS0_CORE1_INTR_ESM0_ESM_INT_HI

Level
R5FSS0_CORE1_INTR_IN_115 115 R5FSS0_CORE1_INTR_ESM0_ESM_INT_LOW

Level
R5FSS0_CORE1_INTR_IN_116 116 R5FSS0_CORE1_INTR_R5SS0_COMMRX_1 R5SS Internal
R5FSS0_CORE1_INTR_IN_117 117 R5FSS0_CORE1_INTR_R5SS0_COMMTX_1 R5SS Internal
R5FSS0_CORE1_INTR_IN_118 118 R5FSS0_CORE1_INTR_R5SS0_CPU0_CTI_INT R5SS Internal
R5FSS0_CORE1_INTR_IN_119 119 R5FSS0_CORE1_INTR_R5SS0_CPU1_CTI_INT R5SS Internal
R5FSS0_CORE1_INTR_IN_120 120 R5FSS0_CORE1_INTR_R5SS0_CPU1_VALFIQ R5SS Internal
R5FSS0_CORE1_INTR_IN_121 121 R5FSS0_CORE1_INTR_R5SS0_CPU1_VALIRQ R5SS Internal
R5FSS0_CORE1_INTR_IN_122 122 R5FSS0_CORE1_INTR_R5SS1_CPU0_PMU_INT R5SS Internal
R5FSS0_CORE1_INTR_IN_123 123 R5FSS0_CORE1_INTR_R5SS1_CPU1_PMU_INT R5SS Internal
R5FSS0_CORE1_INTR_IN_124 124 R5FSS0_CORE1_INTR_MMR_ACC_ERRAGG

Level
R5FSS0_CORE1_INTR_IN_125 125 R5FSS0_CORE1_INTR_R5SS0_LIVELOCK_0 R5SS Internal
R5FSS0_CORE1_INTR_IN_126 126 R5FSS0_CORE1_INTR_R5SS1_LIVELOCK_0 R5SS Internal
R5FSS0_CORE1_INTR_IN_127 127 R5FSS0_CORE1_INTR_R5SS1_LIVELOCK_1 R5SS Internal
R5FSS0_CORE1_INTR_IN_128 128 R5FSS0_CORE1_INTR_RTI_WDT1_NMI

Pulse
R5FSS0_CORE1_INTR_IN_129 129 R5FSS0_CORE1_INTR_SW_IRQ

Pulse
R5FSS0_CORE1_INTR_IN_130 130 R5FSS0_CORE1_INTR_R5SS0_CORE1_FPU_EXP R5SS Internal
R5FSS0_CORE1_INTR_IN_131 131 R5FSS0_CORE1_INTR_DEBUGSS_TXDATA_AVAIL

Level
R5FSS0_CORE1_INTR_IN_132 132 R5FSS0_CORE1_INTR_DEBUGSS_R5SS1_STC_DONE

Pulse
R5FSS0_CORE1_INTR_IN_133 133 R5FSS0_CORE1_INTR_TSENSE_H

Level
R5FSS0_CORE1_INTR_IN_134 134 R5FSS0_CORE1_INTR_TSENSE_L

Level
R5FSS0_CORE1_INTR_IN_135 135 R5FSS0_CORE1_INTR_AHB_WRITE_ERR

Pulse
R5FSS0_CORE1_INTR_IN_136 136 R5FSS0_CORE1_INTR_MBOX_READ_REQ

Level
R5FSS0_CORE1_INTR_IN_137 137 R5FSS0_CORE1_INTR_MBOX_READ_ACK

Level
R5FSS0_CORE1_INTR_IN_138 138 R5FSS0_CORE1_INTR_SOC_TIMESYNCXBAR1_OUT_6

Level/Pulse*
R5FSS0_CORE1_INTR_IN_139 139 R5FSS0_CORE1_INTR_SOC_TIMESYNCXBAR1_OUT_7 Level/Pulse*
R5FSS0_CORE1_INTR_IN_140 140 R5FSS0_CORE1_INTR_SOC_TIMESYNCXBAR1_OUT_8 Level/Pulse*
R5FSS0_CORE1_INTR_IN_141 141 R5FSS0_CORE1_INTR_SOC_TIMESYNCXBAR1_OUT_9 Level/Pulse*
R5FSS0_CORE1_INTR_IN_142 142 R5FSS0_CORE1_INTR_GPIO_INTRXBAR_OUT_18 Level/Pulse*
R5FSS0_CORE1_INTR_IN_143 143 R5FSS0_CORE1_INTR_GPIO_INTRXBAR_OUT_19 Level/Pulse*
R5FSS0_CORE1_INTR_IN_144 144 R5FSS0_CORE1_INTR_GPIO_INTRXBAR_OUT_20 Level/Pulse*
R5FSS0_CORE1_INTR_IN_145 145 R5FSS0_CORE1_INTR_GPIO_INTRXBAR_OUT_21 Level/Pulse*
R5FSS0_CORE1_INTR_IN_146 146 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_0 Level/Pulse*
R5FSS0_CORE1_INTR_IN_147 147 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_1 Level/Pulse*
R5FSS0_CORE1_INTR_IN_148 148 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_2 Level/Pulse*
R5FSS0_CORE1_INTR_IN_149 149 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_3 Level/Pulse*
R5FSS0_CORE1_INTR_IN_150 150 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_4 Level/Pulse*
R5FSS0_CORE1_INTR_IN_151 151 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_5 Level/Pulse*
R5FSS0_CORE1_INTR_IN_152 152 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_6 Level/Pulse*
R5FSS0_CORE1_INTR_IN_153 153 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_7 Level/Pulse*
R5FSS0_CORE1_INTR_IN_154 154 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_8 Level/Pulse*
R5FSS0_CORE1_INTR_IN_155 155 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_9 Level/Pulse*
R5FSS0_CORE1_INTR_IN_156 156 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_10 Level/Pulse*
R5FSS0_CORE1_INTR_IN_157 157 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_11 Level/Pulse*
R5FSS0_CORE1_INTR_IN_158 158 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_12 Level/Pulse*
R5FSS0_CORE1_INTR_IN_159 159 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_13 Level/Pulse*
R5FSS0_CORE1_INTR_IN_160 160 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_14 Level/Pulse*
R5FSS0_CORE1_INTR_IN_161 161 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_15 Level/Pulse*
R5FSS0_CORE1_INTR_IN_162 162 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_16 Level/Pulse*
R5FSS0_CORE1_INTR_IN_163 163 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_17 Level/Pulse*
R5FSS0_CORE1_INTR_IN_164 164 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_18 Level/Pulse*
R5FSS0_CORE1_INTR_IN_165 165 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_19 Level/Pulse*
R5FSS0_CORE1_INTR_IN_166 166 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_20 Level/Pulse*
R5FSS0_CORE1_INTR_IN_167 167 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_21 Level/Pulse*
R5FSS0_CORE1_INTR_IN_168 168 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_22 Level/Pulse*
R5FSS0_CORE1_INTR_IN_169 169 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_23 Level/Pulse*
R5FSS0_CORE1_INTR_IN_170 170 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_24 Level/Pulse*
R5FSS0_CORE1_INTR_IN_171 171 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_25 Level/Pulse*
R5FSS0_CORE1_INTR_IN_172 172 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_26 Level/Pulse*
R5FSS0_CORE1_INTR_IN_173 173 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_27 Level/Pulse*
R5FSS0_CORE1_INTR_IN_174 174 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_28 Level/Pulse*
R5FSS0_CORE1_INTR_IN_175 175 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_29 Level/Pulse*
R5FSS0_CORE1_INTR_IN_176 176 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_30 Level/Pulse*
R5FSS0_CORE1_INTR_IN_177 177 R5FSS0_CORE1_CONTROLSS_INTRXBAR0_OUT_31 Level/Pulse*
R5FSS0_CORE1_INTR_IN_178 178 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_0

Pulse
R5FSS0_CORE1_INTR_IN_179 179 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_1

Pulse
R5FSS0_CORE1_INTR_IN_180 180 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_2

Pulse
R5FSS0_CORE1_INTR_IN_181 181 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_3

Pulse
R5FSS0_CORE1_INTR_IN_182 182 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_4 Pulse
R5FSS0_CORE1_INTR_IN_183 183 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_5 Pulse
R5FSS0_CORE1_INTR_IN_184 184 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_6 Pulse
R5FSS0_CORE1_INTR_IN_185 185 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_7 Pulse
R5FSS0_CORE1_INTR_IN_186 186 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_8 Pulse
R5FSS0_CORE1_INTR_IN_187 187 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_9 Pulse
R5FSS0_CORE1_INTR_IN_188 188 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_10 Pulse
R5FSS0_CORE1_INTR_IN_189 189 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_11 Pulse
R5FSS0_CORE1_INTR_IN_190 190 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_12 Pulse
R5FSS0_CORE1_INTR_IN_191 191 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_13 Pulse
R5FSS0_CORE1_INTR_IN_192 192 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_14 Pulse
R5FSS0_CORE1_INTR_IN_193 193 R5FSS0_CORE1_INTR_PRU_ICSSM0_PR1_IEP0_CMP_INTR_REQ_15 Pulse
R5FSS0_CORE1_INTR_IN_194 194 R5FSS0_CORE1_CPSW0_CPTS_COMP

Level
R5FSS0_CORE1_INTR_IN_195 195 R5FSS0_CORE1_INTR_RESERVED

NA
R5FSS0_CORE1_INTR_IN_196 196 R5FSS0_CORE1_INTR_RESERVED

NA
R5FSS0_CORE1_INTR_IN_197 197 R5FSS0_CORE1_INTR_MCAN4_EXT_TS_ROLLOVER_LVL_INT_0

Level
R5FSS0_CORE1_INTR_IN_198 198 R5FSS0_CORE1_INTR_MCAN4_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_199 199 R5FSS0_CORE1_INTR_MCAN4_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_200 200 R5FSS0_CORE1_INTR_MCAN5_EXT_TS_ROLLOVER_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_201 201 R5FSS0_CORE1_INTR_MCAN5_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_202 202 R5FSS0_CORE1_INTR_MCAN5_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_203 203 R5FSS0_CORE1_INTR_MCAN6_EXT_TS_ROLLOVER_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_204 204 R5FSS0_CORE1_INTR_MCAN6_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_205 205 R5FSS0_CORE1_INTR_MCAN6_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_206 206 R5FSS0_CORE1_INTR_MCAN7_EXT_TS_ROLLOVER_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_207 207 R5FSS0_CORE1_INTR_MCAN7_MCAN_LVL_INT_0 Level
R5FSS0_CORE1_INTR_IN_208 208 R5FSS0_CORE1_INTR_MCAN7_MCAN_LVL_INT_1 Level
R5FSS0_CORE1_INTR_IN_209 209 R5FSS0_CORE1_INTR_R5SS0_CPU0_TMU_LVF Level
R5FSS0_CORE1_INTR_IN_210 210 R5FSS0_CORE1_INTR_R5SS0_CPU0_TMU_LUF Level
R5FSS0_CORE1_INTR_IN_211 211 R5FSS0_CORE1_INTR_HW_RESOLVER Level
R5FSS0_CORE1_INTR_IN_212 212 R5FSS0_CORE1_INTR_FSS_VBUSM_TIMEOUT Level
R5FSS0_CORE1_INTR_IN_213 213 R5FSS0_CORE1_INTR_OTFA_ERROR Level
R5FSS0_CORE1_INTR_IN_214 214 R5FSS0_CORE1_INTR_FOTA_STAT Level
R5FSS0_CORE1_INTR_IN_215 215 R5FSS0_CORE1_INTR_FOTA_STAT_ERR Level
R5FSS0_CORE1_INTR_IN_216 216 R5FSS0_CORE1_INTR_MCSPI5_INTR

Level
R5FSS0_CORE1_INTR_IN_217 217 R5FSS0_CORE1_INTR_MCSPI6_INTR

Level
R5FSS0_CORE1_INTR_IN_218 218 R5FSS0_CORE1_INTR_MCSPI7_INTR

Level
R5FSS0_CORE1_INTR_IN_219 219 R5FSS0_CORE1_INTR_RTI4_INTR_0

Pulse
R5FSS0_CORE1_INTR_IN_220 220 R5FSS0_CORE1_INTR_RTI4_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_221 221 R5FSS0_CORE1_INTR_RTI4_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_222 222 R5FSS0_CORE1_INTR_RTI4_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_223 223 R5FSS0_CORE1_INTR_RTI4_OVERFLOW_INT0 Level
R5FSS0_CORE1_INTR_IN_224 224 R5FSS0_CORE1_INTR_RTI4_OVERFLOW_INT1 Level
R5FSS0_CORE1_INTR_IN_225 225 R5FSS0_CORE1_INTR_RTI5_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_226 226 R5FSS0_CORE1_INTR_RTI5_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_227 227 R5FSS0_CORE1_INTR_RTI5_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_228 228 R5FSS0_CORE1_INTR_RTI5_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_229 229 R5FSS0_CORE1_INTR_RTI5_OVERFLOW_INT0 Level
R5FSS0_CORE1_INTR_IN_230 230 R5FSS0_CORE1_INTR_RTI5_OVERFLOW_INT1 Level
R5FSS0_CORE1_INTR_IN_231 231 R5FSS0_CORE1_INTR_RTI6_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_232 232 R5FSS0_CORE1_INTR_RTI6_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_233 233 R5FSS0_CORE1_INTR_RTI6_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_234 234 R5FSS0_CORE1_INTR_RTI6_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_235 235 R5FSS0_CORE1_INTR_RTI6_OVERFLOW_INT0 Level
R5FSS0_CORE1_INTR_IN_236 236 R5FSS0_CORE1_INTR_RTI6_OVERFLOW_INT1 Level
R5FSS0_CORE1_INTR_IN_237 237 R5FSS0_CORE1_INTR_RTI7_INTR_0 Pulse
R5FSS0_CORE1_INTR_IN_238 238 R5FSS0_CORE1_INTR_RTI7_INTR_1 Pulse
R5FSS0_CORE1_INTR_IN_239 239 R5FSS0_CORE1_INTR_RTI7_INTR_2 Pulse
R5FSS0_CORE1_INTR_IN_240 240 R5FSS0_CORE1_INTR_RTI7_INTR_3 Pulse
R5FSS0_CORE1_INTR_IN_241 241 R5FSS0_CORE1_INTR_RTI7_OVERFLOW_INT0 Level
R5FSS0_CORE1_INTR_IN_242 242 R5FSS0_CORE1_INTR_RTI7_OVERFLOW_INT1 Level
R5FSS0_CORE1_INTR_IN_243 243 R5FSS0_CORE1_INTR_R5SS0_CPU0_RL2_ERR Level
R5FSS0_CORE1_INTR_IN_244 244 R5FSS0_CORE1_INTR_R5SS0_CPU1_RL2_ERR Level
R5FSS0_CORE1_INTR_IN_245 245 R5FSS0_CORE1_INTR_R5SS1_CPU0_RL2_ERR Level
R5FSS0_CORE1_INTR_IN_246 246 R5FSS0_CORE1_INTR_R5SS1_CPU1_RL2_ERR Level