SPRUJ55 User guide | 德州仪器 TI.com.cn

SPRUJ55D September 2023 – July 2025 AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

13.3.1.3.7.1 Data Buffer

The MMC/SD/SDIO host controller uses a data buffer. This buffer transfers data from one data bus (Interconnect) to another data bus (SD, SDIO, or MMC card bus) and vice versa.

The buffer is the heart of the interface and ensures the transfer between the two interfaces (L4 and the card). To enhance performance, the data buffer is completed by a prefetch register and a post-write buffer that are not accessible by the host controller.

The read access time of the prefetch register is faster than the one of the data buffer. The prefetch register allows data to be read from the data buffer at an increased speed by preloading data into the prefetch register.

The entry point of the data buffer, the prefetch buffer, and the post-write buffer is the 32-bit register MMC_DATA. A write access to the MMC_DATA register followed by a read access from the MMC_DATA register corresponds to a write access to the post-write buffer followed by a read access to the prefetch buffer. As a consequence, it is normal that the data of the write access to the MMC_DATA register and the data of the read access to the MMC_DATA register are different.

The number of 32-bit accesses to the MMC_DATA register that are needed to read (or write) a data block with a size of MMC_BLK[10:0] BLEN, and equals the rounded up result of BLEN divided by 4. The maximum block size supported by the host controller is hard-coded in the register MMC_CAPA[17:16] MBL field and cannot be changed.

A read access to the MMC_DATA register is allowed only when the buffer read enable status is set to 1 (MMC_PSTATE[11] BRE); otherwise, a bad access (MMC_STAT[29] BADA) is signaled.

A write access to the MMC_DATA register is allowed only when the buffer write enable status is set to 1 (MMC_PSTATE[10] BWE); otherwise, a bad access (MMC_STAT[29] BADA) is signaled and the data is not written.

The data buffer has two modes of operation to store and read of the first and second portions of the data buffer:

When the size of the data block to transfer is less than or equal to MEM_SIZE/2 (in double buffering), two data transfers can occur from one data bus to the other data bus and vice versa at the same time. The MMC/SD/SDIO controller uses the two portions of the data buffer in a ping-pong manner so that storing and reading of the first and second portions of the data buffer are automatically interchanged from time to time so that data may be read from one portion (for instance, through a DMA read access on the interconnect bus) while data (for instance, from the card) is being stored into the other portion and vice versa. When BLEN is less than or equal to 200h (that is, less or equal to 512Bytes), each of the two portions of the buffer that can be used have a size of BLEN (that is, 32-bits x BLEN div by 4). Not more than this total size of 2 times 32-bits × BLEN div by 4 can be used.
When the size of the data block to transfer is larger than MEM_SIZE/2, only one data transfer can occur from one data bus to the other data bus at a time. The MMC/SD/SDIO host controller uses the entire data buffer as a single portion. In this mode, a bad access (MMC_STAT[29] BADA) is signaled when two data transfers occur from one data bus to the other data bus and vice versa at the same time.

CAUTION:

The MMC_CMD[4] DDIR bit must be configured before a transfer to indicate the direction of the transfer.

Figure 13-133 shows the buffer management for writing and Figure 13-134 shows the buffer management for reading.

Figure 13-133 Buffer Management for a Write

Figure 13-134 Buffer Management for a Read