SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The Error Interrupt Mask Clear Register is used to disable interrupts.
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:3 | Reserved | r | 0x0 | Reserved. Read as 0. |
2 | cmd | r/w1tc | 0x1 |
This field is used to clear the mask for the Command Timeout Error. Read 0 – Interrupt is disabled (mask cleared) 1 – Interrupt is enabled (mask set) Write 0 – No effect 1 – Disable interrupt (mask clear) |
1 | unexp | r/w1tc | 0x1 |
This field is used to clear the mask for the Unexpected Response Error. Read 0 – Interrupt is disabled (mask cleared) 1 – Interrupt is enabled (mask set) Write 0 – No effect 1 – Disable interrupt (mask clear) |
0 | timeout | r/w1tc | 0x1 |
This field is used to clear the mask for the Timeout Interrupt. Read 0 – Interrupt is disabled (mask cleared) 1 – Interrupt is enabled (mask set) Write 0 – No effect 1 – Disable interrupt (mask clear) |