SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
Figure 11-43 shows the Timer Manager integration.
Table 11-83 and Table 11-84 summarize the integration of the module in the device.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
TIMER_MGR0 | PSC0 | GP | LPSC0 | MODSS_CBASS |
TIMER_MGR1 | PSC0 | GP | LPSC0 | MODSS_CBASS |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
TIMER_MGR0 | TIMER_MGR0_ICLK | MODSS_VBUS_D2_CLK | MAIN_SYSCLK0 | Timer Manager0 interface clock |
EON_TICK_EVT | CPTS0_TS_GENF0 | CPTS0 | Timer Manager0 asynchronous tick event | |
TIMER_MGR1 | TIMER_MGR1_ICLK | MODSS_VBUS_D2_CLK | MAIN_SYSCLK0 | Timer Manager1 interface clock |
EON_TICK_EVT | CPTS0_TS_GENF1 | CPTS0 | Timer Manager1 asynchronous tick event | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
TIMER_MGR0 | TIMER_MGR0_RST | MODSS_RST | LPSC0 | Timer Manager0 hardware reset |
TIMER_MGR1 | TIMER_MGR1_RST | MODSS_RST | LPSC0 | Timer Manager1 hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
TIMER_MGR0 | TIMERMGR0_EVT | INTR_AGGR0 SEVI | INTR_AGGR0 | Timer expiration events ×1024 | ETL |
TIMER_MGR1 | TIMERMGR1_EVT | INTR_AGGR1 SEVI | INTR_AGGR1 | Timer expiration events ×1024 | ETL |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
TIMER_MGR0 | - | - | - | No PDMA channels to external DMA engines | - |
TIMER_MGR1 | - | - | - | No PDMA channels to external DMA engines | - |